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Freescale Semiconductor MPC5200 Application Note

Ata interface
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Freescale Semiconductor
Application Note
MPC5200 ATA Interface
by: Martin Nykodym
Transportation Standard Products Group
1
Introduction
This application note describes initialization, general
rules, programming model and performance analysis for
the MPC5200 ATA interface, mainly from a software
perspective. The main focus is to help system architects
understand which mode under what circumstances is
optimal for the final product. Detailed software examples
can be found on the publicly available CD with sample
code for the MPC5200. The MPC5200B microcontroller
1
is based on an e300
core using the PowerPC
instruction set.
The ATA interface is used to connect:
•
Hard disks
•
CD-ROMs
•
DVDs
•
Flash storage devices
The MPC5200 ATA interface is fully compatible with
ATA/ATAPI-4 specification (AT Attachment with Packet
Interface Extension, ANSI NCITS 317-1998) supporting
all three groups of modes:
1. e300, 603e, and G2LE are synonymous.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 Electrical Characteristics . . . . . . . . . . . . . . . . 3
2.2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 IO Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Byte Ordering. . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Register Addressing . . . . . . . . . . . . . . . . . . . 5
2.6 Sector Addressing . . . . . . . . . . . . . . . . . . . . . 6
2.7 ATA Programming Model . . . . . . . . . . . . . . . 6
2.8 Host Initialization . . . . . . . . . . . . . . . . . . . . . . 9
2.9 Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Performance Analysis . . . . . . . . . . . . . . . . . . . . . 14
TM
4
Literature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AN3223
Rev. 0, 2/2006

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Summary of Contents for Freescale Semiconductor MPC5200

  • Page 1: Table Of Contents

    2.2 Signals ......4 the MPC5200 ATA interface, mainly from a software 2.3 IO Cable.

  • Page 2: Ata Interface

    The MPC5200 ATA interface is clocked by the IPBI clock of the MPC5200 processor (66/132 MHz). MPC5200 acts as an ATA host and can control up to two ATA devices as defined in ATA/ATAPI-4 specification. Pin ATA_ISOLATION of the MPC5200 (not defined as a signal by ATA/ATAPI-4 spec) connects to the transceiver’s OE pin to control the direction (high = write to drive,...

  • Page 3: Electrical Characteristics

    Data bus bit 9 ATA_DATA_9 <> Data bus bit 10 DD10 ATA_DATA_10 <> Data bus bit 11 DD11 ATA_DATA_11 <> Data bus bit 12 DD12 ATA_DATA_12 <> Data bus bit 13 DD13 ATA_DATA_13 <> MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...

  • Page 4: Io Cable

    80-pin grounded cable helps to avoid problems with noise and inductance although 40-pin cable is sufficient for modes up to UDMA-2 as in the ATA/ATAPI-4 spec. Also ATA/ATAPI-4 compliant termination is a must; otherwise, CRC checksum error may randomly occur. MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...

  • Page 5: Byte Ordering

    Register Addressing This section describes the generation of the actual address (CSn-, DAn) that is present on the physical ATA interface to address an ATA drive register by means of operations on internal registers of the MPC5200. Table 4 shows how internal registers are decoded to ATA bus operations.

  • Page 6: Sector Addressing

    The MPC5200 host system may select either CHS translation addressing or LBA addressing on a command-by-command basis by using the LBA bit in the ATA drive device/head register. The LBA bit must be set if the host uses LBA addressing mode. The MPC5200 allows 27-bit LBA addressing per device.
  • Page 7 Execute ATA command according specified protocol Figure 2. MPC5200 ATA Programming Model A BestComm task loader is needed if there is some peripheral requiring DMA transfer over the FIFOs to/from a peripheral (ATA MDMA/UDMA, Ethernet, LocalPlus, PCI, etc.). The BestComm image is downloaded and initialized only once, right after booting, due to the static content of the BestComm image (image means BestComm binary firmware).
  • Page 8 Figure 3. MDMA/UDMA BestComm Driven Data Transfer The BestComm C-API is not resident software. It is a piece of software statically linked to the driver that includes a set of standardized function calls. MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...

  • Page 9: Host Initialization

    (See the XLB Arbiter chapter in the MPC5200 User’s Manual for details.) Host Initialization The MPC5200 ATA host initialization covers three different groups of steps: 1. ATA common initialization — Set ATA chip select in GPS port configuration register — Read IPBI clock speed in CDM configuration register (66 or 132 MHz) needed for timing registers) —...
  • Page 10 ATA Interface intended to help software engineers understand how to initialize the MPC5200 ATA interface and how to execute standard commands. NOTE Flash storage media require a different set of commands that are not described in this application note. It is recommended to first read the identify table for each ATA device found on the ATA bus.
  • Page 11 Wait for ATA interrupt – indicates that the device has accepted the command SET FEATURES 8. DEV - The Device Selection bit in ATA drive device/head register specifies which device is selected, 0 or 1. MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...
  • Page 12 Bestcomm. In the case of Bestcomm when snooping is not used, cache needs to be flushed first (entire write buffer) 7. Wait for ATA interrupt – indicates that the data has been written by the device MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...
  • Page 13 Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register b) Write ATA drive device/head register with appropriate DEV bit and LBA bit c) Wait 400 ns d) Wait for BSY=0 and DRQ = 0 in ATA drive alternate status register MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...

  • Page 14: Performance Analysis

    The interface is capable of accepting commands while waiting for the spindle to reach operating speed. Delay is roughly hundreds of milliseconds — Idle mode – See technical documentation for the ATA device. MPC5200 ATA Interface, Rev. 0 Freescale Semiconductor...
  • Page 15 • MPC5200 timing granularity – The MPC5200 ATA interface is clocked by the IPBI clock (66/132 MHz). The ATA/ATAPI-4 specification defines minimum values for cycle time, setup time, and hold time. Minimum values for timing registers are specified in IPBI clock cycles and need to be rounded up;...
  • Page 16 UDMA-4 66 MBytes/sec mode. The programming model is the same as for UDMA-2. The impact of all the above possible performance considerations is more visible because of higher speed. 11.Reading subsequent sectors from hard disk with enabled look-ahead feature, the worst scenario for MPC5200 core load MPC5200 ATA Interface, Rev. 0...

  • Page 17: Literature

    Literature Literature • MPC5200UM, MPC5200 User’s Manual (www.freescale.com) • MPCFPE32B, Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture) (www.freescale.com) • G2CORERM, G2 Core Reference Manual (www.freescale.com) • ATA/ATAPI-4, AT Attachment with Packet Interface Extension, ANSI NCITS 317–1998 (www.t13.org/technical/d98121r0.pdf) •...

  • Page 18: Appendix A Mpc5200 Ata Register Summary

    MPC5200 ATA Register Summary Appendix A MPC5200 ATA Register Summary Table A1. MPC5200 ATA Host Registers Register Acronym Offset Size [Bits] ATA host configuration ata_config MBAR+0x3A00 ATA host status ata_status MBAR+0x3A04 NOTES: Acronyms use terminology such as ata.h in freely distributed software examples.
  • Page 19 MPC5200 ATA Register Summary Table A4. MPC5200 ATA Drive Registers Register Acronym Offset Size [Bits] Mode ATA drive device control ata_drive_ctrl MBAR+0x3A5C write-only ATA drive alternate status read-only ATA drive data ata_drive_data MBAR+0x3A60 ATA drive features ata_drive_ftr MBAR+0x3A64 write-only ATA drive error...
  • Page 20 Europe, Middle East, and Africa: Freescale Semiconductor assume any liability arising out of the application or use of any Freescale Halbleiter Deutschland GmbH product or circuit, and specifically disclaims any and all liability, including without Technical Information Center limitation consequential or incidental damages.

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