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ASAHI AKD4671-B Manual

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AKD4671 is an evaluation board for the AK4671, stereo CODEC with built-in Microphone-Amplifier,
Receiver-Amplifier and Headphone-Amplifier.
The AKD4671 can evaluate A/D converter and D/A converter separately in addition to loopback mode
(A/D → D/A). The AKD4671-B also has the digital audio interface and can achieve the interface with
digital audio systems via opt-connector.
Ordering guide
AKD4671
---
• DIT/DIR with optical input/output
• 10pin Header for Digital Audio I/F, PCM I/F (Baseband, Bluetooth)
• BNC connector for an external clock input
• 10pin Header for serial control mode
Opt Out
TX
AK4114
Opt In
RX
Digital Audio I/F
10Pin Header
Control I/F
10Pin Header
Control I/F
SAR ADC
10Pin Header
Baseband I/F
10Pin Header
Bluetooth I/F
10Pin Header
* Circuit diagram and PCB layout are attached at the end of this manual
<KM089001>
GENERAL DESCRIPTION
Evaluation board for AK4671
(Cable for connecting with printer port of IBM-AT,compatible PC and control
software are packed with this. This control software does not support Windows NT.)
TVDD3
TVDD2
DVDD
DIR
DIT
AK4671
VSS2
VSS1
Figure 1. AKD4671-B Block Diagram
AK4671 Evaluation board Rev.1
FUNCTION
PVDD
SAVDD
AVDD
VSS4
VSS3
GND
- 1 -
AKD4671-B
REG
3.3 V
REG
MIC
Jack
LIN2/3/4
RIN2/3/4
SAIN1/2/3
SAIN3
Jack
[AKD4671-B]
LIN1/RIN1
LOUT1/2/3
ROUT1/2/3
HP
2008 / 03

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Summary of Contents for ASAHI AKD4671-B

  • Page 1 Receiver-Amplifier and Headphone-Amplifier. The AKD4671 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D → D/A). The AKD4671-B also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector.
  • Page 2 PORT7 PORT5 CTRL CTRL Figure 2. AKD4671-B Outline Chart Comment (1) J2, J3 (MINI-JACK) J2 : It is analog signal input Jack. The signal is input to LIN1 / RIN1 pins. J3 : It is analog signal output Jack. The signal is output from LOUT2 / ROUT2 pins, and JP17, JP19 should be “short”.
  • Page 3 [AKD4671-B] (6) PORT3, PORT4, PORT 6 (10 pin header) PORT3 : The clock and data of Baseband mode can be inputted and outputted with this connector. PORT4 : The clock and data of DSP can be inputted and outputted with this connector.
  • Page 4 [AKD4671-B] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. (1-1) In case of using the regulator. Set up the jumper pins. JP20 JP22 JP24 JP26 JP27 JP29 JP31 AVDD SAVDD PVDD DVDD TVDD2 TVDD3 VCC2 State...
  • Page 5 [AKD4671-B] (1-2) In case of using the power supply connectors. Set up the jumper pins. JP20 JP22 JP24 JP26 JP27 JP29 JP31 AVDD SAVDD PVDD DVDD TVDD2 TVDD3 VCC2 State Open Open Open Open Open Open Open Open Set up the power supply lines.
  • Page 6 [AKD4671-B] Evaluation mode 1. Audio I/F evaluation mode In case of AK4671 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4671 and AK4114. About AK4671’s audio interface format, refer to datasheet of AK4671. About AK4114’s audio interface format, refer to Table 2 on page 19.
  • Page 7 [AKD4671-B] (1) External Slave Mode When PMPLL bit is “0”, the AK4671 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 384fs, 512fs, 768fs or 1024fs), LRCK (fs) and BICK (≥32fs).
  • Page 8 [AKD4671-B] (1-3) Evaluation of Loop-back using AK4114 <default> X2 (X’tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP48 JP46 JP36 JP33 JP38 JP51 JP35...
  • Page 9 [AKD4671-B] (2) External Master Mode The AK4671 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input via MCKI pin, without using on-chip PLL circuit. The clock required to operate is MCKI (256fs, 384fs, 512fs, 768fs or 1024fs).
  • Page 10 [AKD4671-B] (2-3) Evaluation of Loop-back using AK4114 X’tal (X2) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP36 JP33 JP38 JP51 JP35 BICK_SEL LRCK_SEL SDTI_SEL...
  • Page 11 [AKD4671-B] (3) PLL Slave Mode A reference clock of PLL is selected among the input clocks to MCKI, BICK or LRCK pin. The required clock to the AK4671 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits.
  • Page 12 [AKD4671-B] (3-1-2) Evaluation of Loop-back using AK4114 J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X’tal oscillator should be removed from X2. The jumper pins should be set as the following. JP51...
  • Page 13 [AKD4671-B] (3-2) PLL Reference Clock : BICK or LRCK pin AK4671 DSP or μP MCKO MCKI 32fs or 64fs BCLK BICK LRCK LRCK SDTI SDTO SDTO SDTI (PLL Reference Clock: BICK pin) AK4671 DSP or μP MCKO MCKI ≥ 32fs...
  • Page 14 [AKD4671-B] (3-2-2) Evaluation of D/A using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT4 (DSP). The jumper pins should be set as the following. JP51 JP35 JP33 JP38 JP46 JP36 JP39 SDTI_SEL...
  • Page 15 [AKD4671-B] (4) PLL Master Mode When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit.
  • Page 16 [AKD4671-B] (4-2) Evaluation of Loop-back J12 (EXT) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT4 (DSP). X’tal oscillator should be removed from X2. The jumper pins should be set as the following. JP51 JP35 JP33...
  • Page 17 [AKD4671-B] 2. PCM I/F evaluation mode A reference clock of PLLBT is selected among the input clocks to SYNCA, BICKA, SYNCB or BICKB pin. The required clock to PCM I/F is generated by an internal PLLBT circuit. PLLBT circuit is powered up by PMPCM bit.
  • Page 18 [AKD4671-B] (1) PLLBT reference clock: SYNCA or BICKA pin The PLLBT circuit generates the required clock for PCM I/F from SYNCA or BICKA. Generated clocks are output via SYNCB and BICKB pins. AK4671 Baseband Module 1fs2 SYNCA SYNC ≥ 16fs2...
  • Page 19 [AKD4671-B] JP47 (BICKA PHASE) is jumper which decides polarity of BICKA, “THR” or “INV” should be selected according to the PCM I/F format. JP54 (BICKB PHASE) should be set to “THR”. JP47 JP54 BICKA PHASE BICKB PHASE In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short.
  • Page 20 [AKD4671-B] (2) PLLBT reference clock: SYNCB or BICKB pin The PLLBT circuit generates the required clock for PCM I/F from SYNCB or BICKB. Generated clocks are output via SYNCA and BICKA pins. AK4671 Baseband Module 1fs2 SYNCA SYNC 16fs2 or 32fs2...
  • Page 21 [AKD4671-B] JP54 (BICKB PHASE) is jumper which decides polarity of BICKB, “THR” or “INV” should be selected according to the PCM I/F format. JP47 (BICKA PHASE) should be set to “THR”. JP47 JP54 BICKA PHASE BICKB PHASE In case of loop-back “SDTOA → SDTIA” and “SDTOB → SDTIB”, please set JP50 (SDTOA LOOP) and JP55 (SDTOB LOOP) short.
  • Page 22 [AKD4671-B] DIP Switch set up [S1] (SW DIP-6): Mode setting for AK4671 and AK4114. Name ON (“H”) OFF (“L”) Default DIF2 AK4114 Audio Format Setting DIF1 See Table 2 DIF0 OCKS1 AK4114 Master Clock Setting : See Table 3 CAD0...
  • Page 23 [AKD4671-B] Other jumper pins set up Sub Board [JP1] (RIN2) : RIN2 input. GND : In case of full-differential input. MPWR : MIC-power is supplied to RIN2. OPEN : MIC-power is not supplied to RIN2. <Default> [JP2] (LIN1) : LIN1 input.
  • Page 24 [AKD4671-B] The function of the toggle SW [SW2] (PDN) : Power down of AK4671. Keep “H” during normal operation. [SW1] (DIR) : Power down of AK4114. Keep “H” during normal operation. Keep “L” when AK4114 is not used. Indication for LED [LED1] (ERF) : Monitor INT0 pin of the AK4114.

  • Page 25: Analog Input/Output Circuits

    [AKD4671-B] Analog Input/Output Circuits (1) Input Circuits (1-1) LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit LIN1 RIN1 LIN1/RIN1 LIN2 JP23 LIN2 (short) LIN3 LIN3 LIN4 LIN_SEL LIN4 RIN2 JP25 (short) RIN2 RIN3 RIN3 RIN4 RIN_SEL RIN4 Figure 4. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 Input Circuit LIN2/RIN2, LIN3/RIN3 and LIN4/RIN4 share J5/J7.

  • Page 26: Output Circuits

    [AKD4671-B] (2) Output Circuits LOUT1/ROUT1, LOUT2/ROUT2 and LOUT3/ROUT3 Output Circuit JP16 LOUT3 LOUT3 LOUT LOUT2 LOUT2 LOUT1 LOUT1 LOUT_SEL JP17 HPL JACK (short) 100u JP58 L_16ohm JP19 HPR JACK (short) 100u JP59 JP21 R_16ohm ROUT3 ROUT3 ROUT ROUT2 ROUT2 ROUT1...
  • Page 27 1. Set up the AKD4671-B according to previous term. 2. Connect IBM-AT compatible PC with AKD4671-B by 10-line type flat cable (packed with AKD4671-B). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP.
  • Page 28 [AKD4671-B] Explanation of each dialog 1. [Write Dialog] : Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H”...

  • Page 29: Save] And [Open]

    [AKD4671-B] 4. [Save] and [Open] 4-1. [Save] Save the current register setting data. The extension of file name is “akr”. <Operation flow> Click [Save] Button. Set the file name and push [Save] Button. The extension of file name is “akr”.
  • Page 30 [AKD4671-B] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
  • Page 31 [AKD4671-B] 6. [Function4 Dialog] The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure 9. opens. Figure 8. [F4] window <KM089001> 2008 / 03 - 31 -...
  • Page 32 [AKD4671-B] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 10. Figure 9. [F4] window (2) (2) Click [START] button, then the sequence is executed.
  • Page 33 [AKD4671-B] 7. [Function5 Dialog] The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 11.opens. Figure 10. [F5] window 7-1.
  • Page 34 [AKD4671-B] Figure 11. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The register setting file names assign can be saved. The file name is *.ak5 [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
  • Page 35 [AKD4671-B] 8. [Filter Dialog] This dialog can easily set the AK4671’s programmable filter. A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check frequency response. Window to show to Figure 13 opens when push a [Filter] button .
  • Page 36 [AKD4671-B] 8-1. Setting of a parameter (1) Please set a parameter of each Filter. Item Contents Setting range Sampling Rate Sampling frequency (fs) 7350Hz ≤ fs ≤ 48000Hz FIL3 Cut Off Frequency Stereo separation emphasis filter cut off fs/10000 ≤ Cut Off Frequency ≤...
  • Page 37 [AKD4671-B] 8-2. A calculation of a register A register setting values are displayed when [Register Setting] button is clicked. When any value is set to out of range, error message is displayed, and a calculation of register setting is not executed.
  • Page 38 [AKD4671-B] 8-3.Indication of a frequency characteristic A frequency characteristic is displayed when [Frequency Response] button is clicked. The register values are updated at the same time. If "Frequency Range" is changed, and [UpDate] button is clicked, indication of a frequency characteristic is updated.
  • Page 39 [AKD4671-B] Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure16. When there is no compensation of center frequency Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common) Figure17. When there is compensation of center frequency <KM089001>...
  • Page 40 [AKD4671-B] 9. [5 Band EQ Dialog] This dialog can easily set the AK4671’s 5-Band Equalizer. Figure 18. [5 Band EQ] window When the check box of “5 Band EQ” is checked, 5-Band Equalizer is ON (EQ bit = ”1”). When the slide button is changed, its value is written to the internal register immediately.

  • Page 41: Revision History

    These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
  • Page 42 SDTIA BICKA BICKA SYNCA SYNCA SDTOA SDTOA ROUTN ROUTN ROUTP ROUTP SVDD SVDD 0.033u 0.033u Title Title Title AKD4671-B AKD4671-B AKD4671-B 4670_PDN CSN/CAD0 CDTI/SDA 4670_DVDD 4670_SDTIA 4670_SYNCA ROUTN SVDD Size Size Size Document Number Document Number Document Number AK4671 AK4671...
  • Page 43 (short) (short) D3V1 D3V1 T45_OR T45_OR (short) (short) DGND1 DGND1 T45_BK T45_BK Title Title Title AKD4671-B AKD4671-B AKD4671-B Size Size Size Document Number Document Number Document Number Power Supply, I/O Power Supply, I/O Power Supply, I/O Date: Date: Date: Wednesday, March 26, 2008...
  • Page 44 0.1u 0.1u DGND 74HC4040 74HC4040 LRCKA EXT_LRCKA LRCKB EXT_LRCKB JP45 JP45 LRCK2_SEL LRCK2_SEL Title Title Title AKD4671-B AKD4671-B AKD4671-B Size Size Size Document Number Document Number Document Number CLOCK CLOCK CLOCK Date: Date: Date: Wednesday, March 26, 2008 Wednesday, March 26, 2008...
  • Page 45 SDTO 0.1u 0.1u 0.1u 0.1u 4114_LRCK 4114_MCKO PORT2 PORT2 0.1u 0.1u TOTX141 TOTX141 Title Title Title AKD4671-B AKD4671-B AKD4671-B Size Size Size Document Number Document Number Document Number DIR/DIT DIR/DIT DIR/DIT Date: Date: Date: Wednesday, March 26, 2008 Wednesday, March 26, 2008...
  • Page 46 JP55 JP55 SDTOB LOOP SDTOB LOOP SDTIB VCCA VCCB 0.1u 0.1u 0.1u 0.1u 74AVC4T245 74AVC4T245 Title Title Title AKD4671-B AKD4671-B AKD4671-B Size Size Size Document Number Document Number Document Number LOGIC LOGIC LOGIC Date: Date: Date: Wednesday, March 26, 2008...