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Sony HDR-HC5 Service Manual page 16

Digital hd video camera recorder
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1
2
3
4
VC-500 BOARD (6/20)
A
HDV STREAM PROCESS
XX MARK:NO MOUNT
: Voltage measurement of the CSP ICs
and the Transistors with
mark, are
not possible.
B
C
D
FLAT_SYNC_FYO0
C2714
4.7u
L2704
A_1.2V
C2717
0.1u
10uH
L2703
C2716
10uH
A_2.8V
0.1u
RECDT
E
C2713
4.7u
PD01
F
PD06
XPEN0
XIACC0
DXXA01_SIM
DXXA04_SIM
DXXA07_SIM
D24A00_SIM
D30A06_SIM
ERE
EBS[1]
EBS[6]
ERDY
G
THCRQ_FHDI
RYO2_DEFLD
HYI_PLL27IN
H
I
J
K
C2710
0.33u
C2711
0.1u
C2709
XX
L
M
A_1.2V
N
A_2.8V
R2774
D_2.8V
XX
D_2.8V
R2780
(19/20)
XX
D_1.5V
D_1.5V
R2778
XX
D_1.2V_K
D_1.2V_K
R2776
O
XX
REG_GND
05
HDR-HC5/HC5E/HC7/HC7E_L3
5
6
7
8
9
L2702
10uH
C2718
C2708
0.1u
4.7u
E7
VSS
E6
VSS
F6
FLAT_SYNC
G6
PCOR
H6
VSS
J6
VSS
K6
ADDT2
L6
VSS
M6
VSS
N6
PLL1VDD
P6
VSS
R6
AVH
T6
N.C
U6
VSS
V6
PLLMSK
W6
RECDT
Y6
T2DT0
Y7
VSS
Y8
T2DT5
Y9
T2DT9
Y10
T2DT13
Y11
T2DT18
Y12
T2DT20
Y13
T2DT22
Y14
T2DT25
Y15
T2DT27
Y16
T2DT33
Y17
T1DT1
Y18
VSS
Y19
T1DT9
Y20
T1DT31
W20
T1DT34
V20
ILDT1
U20
ILDT6
T20
VSS
R20
ILXPEN
P20
IXPACC
N20
MCADR1
M20
MCADR4
L20
MCADR7
K20
MCDA0
J20
MCDA6
H20
VSS
G20
VSS
F20
VSS
F19
ERDYO
F18
EBS1
F17
EBS6
F16
ERDYI
IC2701
F15
VSS
F14
PIPESTAT1
F13
TRACEPKT0
HDV STREAM PROCESSOR,
F12
TRACEPKT3
MUX/DEMUX,
F11
TRACEPKT7
DV SIGNAL PROCESSOR
F10
VSS
IC2701
F9
THCRQ
MB8AA1121BGL-G-ERE1
F8
YI2
F7
HYO
G7
K10
L10
M10
N10
P10
R10
T10
T11
T12
T13
T14
T15
T16
R16
P16
N16
M16
L16
K16
K15
K14
K13
K12
K11
L11
M11
N11
P11
R11
R12
R13
R14
R15
P15
N15
M15
L15
L14
L13
L12
M12
N12
P12
P13
P14
N14
M14
M13
N13
C2722
C2721
C2723
C2724
C2719
C2725
C2720
4.7u
0.1u
4.7u
0.1u
4.7u
0.1u
4.7u
10
11
12
13
14
C2706
R2708
XX
XX
C2712
XX
T2DT35
AC15
T2DT29
AC14
T2DT26
AC13
T2DT19
AC12
AC11
T2DT17
T2DT11
AC10
T2DT8
AC9
T2DT4
AC8
T2DT1
AC7
TSTMODE0
AC6
T2IO
AC5
TCK18M
AC4
T2SEL6
AC3
TCK83M
AB3
T2SEL5
AA3
T2SEL1
Y3
T2SEL0
W3
RECA2
V3
RECA1
U3
PLLSW
T3
N.C
R3
R2711
N.C
P3
100
PBCK
N3
BCK
M3
VPD
L3
ADDT0
K3
PLLRST
J3
VDDH_3
H3
R2732
0
FLD
G3
VLAT_SYNC
F3
ADATAIN1
E3
ADATAOUT1
D3
VSS
C3
SRCPIC
B3
YO3
B4
YO1
B5
CO3
B6
VDDL
B7
VDDH_3
B8
YI1
B9
HCI
B10
CI0
B11
VDDH_3
B12
VDDL
B13
VDDH_3
B14
VDDL
B15
AUDAI
B16
EBS7
B17
EBS2
B18
AUDAO
B19
VDDH_15
B20
VDDH_3
B21
JTCK
B22
JTMS
B23
VDDL
B24
TRRV
C24
TRRT
D24
FRRV
E24
R2735
MCDVCS
F24
0
VDDH_3
G24
XRST1
H24
VDDH_3
J24
MCDA5
K24
MCDA1
L24
MCADR10
M24
VDDL
N24
MCWRX
P24
HTM1
R24
VDDL
T24
CL2702
U24
ILDT7
ILDT2
V24
T1DT35
W24
T1DT30
Y24
VDDH_3
AA24
T1DT26
AB24
T1DT24
AC24
T1DT23
AD24
T1DT18
AD23
T1DT17
AD22
T1DT15
AD21
T1DT13
AD20
VDDL
AD19
T1DT8
AD18
CL2703
VDDH_3
AD17
T1DT0
AD16
T2DT34
AD15
T2DT30
AD14
VDDL
AD13
VDDL
AD12
T2DT16
AD11
T2DT12
AD10
VDDH_3
AD9
T2DT6
AD8
VDDH_3
AD7
TSTMODE1
AD6
TSTOUT
AD5
T2SEL9
AD4
T2SEL8
AD3
T2SEL7
AD2
T2SEL4
AC2
T2SEL3
AB2
T2SEL2
AA2
VDDT
Y2
VDDH_3
W2
VDDL
V2
VDDT
U2
VDDH_3
T2
N.C
R2
R2717
0
R2718
XX
4-12
15
16
17
18
PCLK0
PCLK0
IDIR0
IDIR0
PD00
PD00
PD01
PD01
PD02
PD02
PD03
PD03
PD04
@042
PD04
PD05
PD05
(7/20)
PD06
PD06
PD07
PD07
XPEN0
XPEN0
XIACC0
XIACC0
FCLR0
FCLR0
FR1
FR1
RECA2
RECA1
CK64FSO
R2720
100k
IC_2101_FLD27MF
VLAT_SYNC_FCI
ADATAIN1
ADATAOUT1
IC_2101_SRCH
RYI3_DE3
RYI1_DE1
RCI3_DE7
RYO1_DEVD
HCO_FYI1
RCO0_EDHD
AUDAI
EBS[7]
EBS[2]
AUDAO
CK27MFO1
CK27MFO1
ADATAIN0
@022
TRRV
ADATAIN0
TRRT
ADATAIN1
ADATAIN1
FRRV
XCS_IC_2701_DV
R2709
C2707
1k
XX
XRST_IC_2701_1
D29A05_SIM
IC_2101_SRCH
D25A01_SIM
IC_2101_SRCH
DXXA10_SIM
IC_2101_PCRERR
IC_2101_PCRERR
WR01_SIM
IC_2101_FLD27MF
IC_2101_FLD27MF
HYO_SLGATE
HYO_SLGATE
PD07
PD02
RYO0_DEHD
RYO0_DEHD
RYO1_DEVD
RYO1_DEVD
RYO2_DEFLD
RYO2_DEFLD
RYO3_SGOUT
RYO3_SGOUT
HCO_FYI1
HCO_FYI1
RCO0_EDHD
RCO0_EDHD
RCO1_EDVD
RCO1_EDVD
RCO2_EDFLD
RCO2_EDFLD
RCO3_FRMREF
RCO3_FRMREF
HYI_PLL27IN
HYI_PLL27IN
RYI0_DE0
RYI0_DE0
RYI1_DE1
RYI1_DE1
RYI2_DE2
RYI2_DE2
RYI3_DE3
RYI3_DE3
C2726
0.1u
HCI_FYI0
HCI_FYI0
C2727
0.1u
RCI0_DE4
RCI0_DE4
C2728
0.1u
RCI1_DE5
RCI1_DE5
C2729
RCI2_DE6
RCI2_DE6
0.1u
RCI3_DE7
C2730
RCI3_DE7
0.1u
MFLG_QRST
C2731
MFLG_QRST
0.1u
C2732
TFS_FCO
0.1u
TFS_FCO
C2733
THYRQ_FVDI
0.1u
THYRQ_FVDI
THCRQ_FHDI
THCRQ_FHDI
VLAT_SYNC_FCI
VLAT_SYNC_FCI
FLAT_SYNC_FYO0
FLAT_SYNC_FYO0
C2734
VLAT_IN_FYO1
0.1u
VLAT_IN_FYO1
FS_EDGE_REF
FS_EDGE_REF
FRAT_REFO
FRAT_REFO
C2735
0.1u
ADATAOUT0
ADATAOUT0
ADATAOUT1
ADATAOUT1
CK64FSO
CK64FSO
@032
CKFSO
CKFSO
19
20
21
(12/20)
@043
SWP
(14/20)
SWP
(17/20)
WR01_SIM
WR01_SIM
RDX_SIM
RDX_SIM
D31A07_SIM
D31A07_SIM
D30A06_SIM
@030
D30A06_SIM
D29A05_SIM
D29A05_SIM
(4/20)
D28A04_SIM
D28A04_SIM
(5/20)
D27A03_SIM
D27A03_SIM
(7/20)
D26A02_SIM
(17/20)
D26A02_SIM
D25A01_SIM
D25A01_SIM
D24A00_SIM
D24A00_SIM
DXXA07_SIM
DXXA07_SIM
DXXA06_SIM
DXXA06_SIM
DXXA05_SIM
DXXA05_SIM
DXXA04_SIM
@044
DXXA04_SIM
DXXA03_SIM
DXXA03_SIM
(7/20)
DXXA02_SIM
DXXA02_SIM
(17/20)
DXXA01_SIM
DXXA01_SIM
DXXA00_SIM
DXXA00_SIM
TRRT
TRRT
DXXA09_SIM
DXXA09_SIM
DXXA08_SIM
@031
DXXA08_SIM
FRRV
FRRV
(4/20)
DRP
DRP
(17/20)
TRRV
TRRV
DXXA10_SIM
DXXA10_SIM
ATF_LATCH
ATF_LATCH
SCWIN
SCWIN
@045
XCS_IC_2701_DV
XCS_IC_2701_DV
XCS_IC_2701_HD
XCS_IC_2701_HD
(17/20)
XRST_IC_2701_DV
XRST_IC_2701_DV
XRST_IC_2701_1
XRST_IC_2701_1
XRST_IC_2701_2
XRST_IC_2701_2
(4/20)
(5/20)
AUDAI
AUDAI
AUENI
AUENI
AUDAO
AUDAO
AUENO
@017
AUENO
KCLK
KCLK
(4/20)
EBS[0]
EBS[0]
EBS[1]
EBS[1]
@041
EBS[2]
EBS[2]
EBS[3]
(5/20)
EBS[3]
EBS[4]
EBS[4]
EBS[5]
EBS[5]
EBS[6]
EBS[6]
EBS[7]
EBS[7]
ERDY
ERDY
ERE
ERE
RECA1
RECA1
RECA2
RECA2
@046
RECCK
RECCK
RECDT
(12/20)
RECDT
(4/20)
RFIN
RFIN
(5/20)
(8/20)
(11/20)
VC-500 (6/20)

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