Denon TU-1800DAB Service Manual page 11

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AD1852JRS (IC102)
DGND
MCLK
CLATCH
CCLK
CDATA
NC
192/48
ZEROR
DEEMP
96/48
AGND
OUTR+
OUTRÐ
FILTR
TERMINAL FUNCTION
Pin Input/Output
1 I
2 I
3 I
4 I
5 I
6
7 I
TE 8 O
L 13942296513
9 I
10 I
11, 15 I
12 O
13 O
14 O
16 O
17 O
18 I
19
20 I
21 I
22 O
23 I
24 I
25 I
26 I
27 I
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28 I
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1 28 DVDD
2 27 SDATA
BCLK
3
26
LRCLK
4 25
5
24 RESET
MUTE
6 23
AD1852
7 ZEROL
22
TOP VIEW
(Not to Scale)
IDPM0
8 21
IDPM1
9 20
FILTB
10
19
AVDD
11 18
12 OUTL+
17
OUTLÐ
13 16
14
15 AGND
Pin Name Description
DGND Digital Ground.
MCLK Master Clock Input. Connect to an external clock source at either 256 F
512 F , 768 F
S
CLATCH L atch Input for Control Data. This input is rising-edge sensitive.
CCLK Control Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
CDATA Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used
for specifying channel-specific attenuation and mute.
N C N o Connect.
192/48 Selects 48 kHz (LO) or 192 kHz Sample Frequency.
ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used
to impose a 50µs/15 µs response characteristic on the output audio spectrum at an
assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.
96/48 Selects 48 kHz (LO) or 96 kHz Sample Frequency.
AGND Analog Ground.
OUTR+ Right Channel Positive Line Level Analog Output.
OUTRÐ Right Channel Negative Line Level Analog Output.
FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10 µF and 0.1 µF capacitors to the AGND.
OUTLÐ L eft Channel Negative Line Level Analog Output.
OUTL+ Left Channel Positive Line Level Analog Output.
AVDD Analog Power Supply. Connect to Analog 5 V Supply.
Filter Capacitor Connection. Connect 10 µF capacitor to AGND (Pin 15).
FILTB
IDPM1 Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
IDPM0 Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
ZEROL Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
MUTE Mute. Assert HI to mute both stereo analog outputs. DeassertLO for normal operation.
RESET Reset. The AD1852 is reset on the rising edge of this signal. The serial control port
registers are reset to the default values. Connect HI for normal operation.
L /RCLK Left/ Right Clock Input for Input Data. Must run continuously.
BCLK Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a
burst fashion.
SDATA Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
x DVDD ao Digital Power Supply Connect to digital 5 V supply.
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TU-1800DAB
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