LG 32LE5500 Service Manual page 43

Serial Flash
IC9000
MX25L4005CM2I-12G
R9000 10
CS# 8 VCC
FRC_SPI_CZ 1
R9001 10 SO 7 HOLD#
2
FRC_SPI_DO
R9002 10K
WP# 6 SCLK
3
GND 5 SI
4
EAN61009401
URSA3_FLASH_MACRONIX
AVDD_PLL
+3.3V_MEMC
AVDD
+3.3V_MEMC
L9004
CIC21J501NE
L9005
CIC21J501NE
C9004 C9009
10uF 0.1uF
C9019
10uF
AVDD_MEMPLL AVDD_LVDS
+3.3V_MEMC
+3.3V_MEMC
L9000
L9006
CIC21J501NE
CIC21J501NE
C9000 C9005
10uF 0.1uF
VDDP
+3.3V_MEMC
L9001
CIC21J501NE
C9006 C9010 C9013 C9016
C9001
10uF 0.1uF 0.1uF 0.1uF
10uF
AVDD_DDR
+1.5V_MEMC
L9002
CIC21J501NE
C9007 C9011 C9014 C9017
C9002
10uF 0.1uF 0.1uF 0.1uF
10uF
VDDC
+1.26V_MEMC
L9003
CIC21J501NE
C9008 C9012 C9015 C9018
C9003
10uF 0.1uF 0.1uF 0.1uF
10uF
P9000
12505WS-04A00
1
22
2
22
3
4
5
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Downloaded from www.Manualslib.com
+3.3V_MEMC
IC9000-*1
W25X40BVSSIG
CS VCC
1 8
DO[IO1] HOLD
2 7
WP CLK
3 6
GND DI[IO0]
4 5
URSA3_FLASH_WINBOND_NEW
R9005 10
FRC_SPI_CK IC9000-*2
W25X40VSSIG
R9006 10
FRC_SPI_DI
CS VCC
1 8
DO HOLD
2 7
WP CLK
3 6
GND DIO
4 5
EAN35097301
URSA3_FLASH_WINBOND_OLD
FRC_A[0-12]
C9024 C9029 C9032
10uF 0.1uF 0.1uF
FRC_BA0
FRC_BA1
FRC_BA2
C9025 C9030 C9033 C9034 C9035
C9020
10uF 0.1uF 0.1uF 0.1uF 0.1uF
10uF FRC_MCLK
FRC_MCLKB
FRC_CKE
FRC_ODT
FRC_RASB
FRC_CASB
FRC_WEB
FRC_DDR3_RESETB
C9021 C9026
0.1uF 0.1uF
FRC_DQSL
FRC_DQSU
FRC_DQSLB
FRC_DQSUB
FRC_DML
FRC_DMU
C9022 C9027 C9031
0.1uF 0.1uF 0.1uF
FRC_DQL[0-7]
FRC_DQU[0-7]
C9023
0.1uF
URSA3_SDA
R9003
URSA3_SCL
R9004
SCL3_3.3V
22 R9007
SDA3_3.3V
22 R9008
OPT
URSA3_SCL SCL1_3.3V
22 R9009
OPT
URSA3_SDA SDA1_3.3V
22 R9010
manuals search engine
C9038
22pF
X9000
R9017 R9023
100 100
R9018 R9024
100 100
R9019 R9025
100 100
R9020 R9026
100 100
R9021 R9027
100 100
R9022 R9028
100 100
FRC_A[0] E2
DDR3_A0/DDR2_NC
FRC_A[1] U6
DDR3_A1/DDR2_A6
FRC_A[2] E3
DDR3_A2/DDR2_A7
FRC_A[3] G2
DDR3_A3/DDR2_A1
FRC_A[4] R4
DDR3_A4/DDR2_CASZ
FRC_A[5] G1
DDR3_A5/DDR2_A10
FRC_A[6] U5
DDR3_A6/DDR2_A0
FRC_A[7] F3
DDR3_A7/DDR2_A5
FRC_A[8] T5
DDR3_A8/DDR2_A2
FRC_A[9] F1
DDR3_A9/DDR2_A9
FRC_A[10] R6
DDR3_A10/DDR2_A11
FRC_A[11] R5
DDR3_A11/DDR2_A4
FRC_A[12] T6
DDR3_A12/DDR2_A8
G3
DDR3_BA0/DDR2_BA2
U4
DDR3_BA1/DDR2_ODT
E1
DDR3_BA2/DDR2_A12
U1
DDR3_MCLK/DDR2_MCLK
U2
DDR3_MCLKZ/DDR2_MCLKZ
T4
DDR3_CKE/DDR2_RASZ
H2
DDR3_ODT/DDR2_BA1
J1
DDR3_RASZ/DDR2_WEZ
H3
DDR3_CASZ/DDR2_CKE
H1
DDR3_WEZ/DDR2_BA0
F2
DDR3_RESET/DDR2_A3
LGE7378A[FRC_TCON_URSA3]
M3
DDR2_DQS0/DDR3_DQS0
N2
DDR2_DQS1/DDR3_DQS1
N1
DDR2_DQSB0/DDR3_DQSB0
N3
DDR2_DQSB1/DDR3_DQSB1
R2
DDR2_DQ7/DDR3_DQM0
K3
DDR2_DQ11/DDR3_DQM1
FRC_DQL[0] K2
DDR2_DQ6/DDR3_DQ0
FRC_DQL[1] R3
DDR2_DQ0/DDR3_DQ1
FRC_DQL[2] K1
DDR2_DQ1/DDR3_DQ2
FRC_DQL[3] T1
DDR2_DQ2/DDR3_DQ3
FRC_DQL[4] J2
DDR2_DQ4/DDR3_DQ4
FRC_DQL[5] T3
DDR2_NC/DDR3_DQ5
FRC_DQL[6] J3
DDR2_DQ3/DDR3_DQ6
FRC_DQL[7] T2
DDR2_DQ5/DDR3_DQ7
FRC_DQU[0] P2
DDR2_DQ8/DDR3_DQ8
FRC_DQU[1] L3
DDR2_DQ14/DDR3_DQ9
FRC_DQU[2] R1
DDR2_DQ13/DDR3_DQ10
FRC_DQU[3] L1
DDR2_DQ12/DDR3_DQ11
FRC_DQU[4] P1
DDR2_DQ15/DDR3_DQ12
FRC_DQU[5] L2
DDR2_DQ9/DDR3_DQ13
FRC_DQU[6] P3
DDR2_DQ10/DDR3_DQ14
FRC_DQU[7] M1
DDR2_DQM1/DDR3_DQ15
M2
DDR2_DQM0/DDR3_NC
R9011 100 C9
I2CM_SDA
R9012 100 D9
I2CM_SCL
100 P7
R9013
I2CM_SDA2_L
100 N8
R9014
I2CM_SCL2_L
100 P9
R9015
I2CM_SDA2_R
100 N10
R9016
I2CM_SCL2_R
AVDD AVDD_DDR AVDD_LVDS AVDD_PLL VDDC
AVDD_MEMPLL
VDDC
L9007
CIC21J501NE
C9036 C9037
0.1uF
10uF
Separate DVDD_DDR Power
C9039
HIGH
FRC OPTION LOW
22pF
K14
NON_MIRROR MIRROR
T10 LVDS MINI_LVDS
12MHz
R9029 R10
GIP NON_GIP
1M
R9
SCAN_OFF SCAN_ON
U10
LD NON_LD
+3.3V_MEMC FRC_CONF0
IC9001
URSA3
VDDP
LD_SCAN
SCAN_BLK2 R9038
100
LD_SCAN
R9039 100
SCAN_BLK1/OPC_OUT
+3.3V_MEMC
R9037 0
DPM_A
MINI_LVDS
SW9000
JTP-1127WEM
1 2
3 4
R9041
820
B14
RXB0+
A0P/RV0+
A14
A0M/RV0- RXB0-
C14
A1P/RV1+ RXB1+
C15
RXB1-
A1M/RLV1-
A15
A2P/RV2+ RXB2+
B15
A2M/RV2- RXB2-
B16
RXBCK+
ACKP/R3+
A16
ACKM/RV3- RXBCK-
A17
A3P/RV4+ RXB3+
B17
A3M/RV4- RXB3-
C16
A4P/RV5+ RXB4+
C17
RXB4-
A4M/RV5-
D16
B0P/RV6+ RXA0+
D17
RXA0-
B0M/RV6-
D15
B1P/RV7+ RXA1+
E15
B1M/RV7- RXA1-
F16
B2P/RV8+ RXA2+
F17
B2M/RV8- RXA2-
F15
RXACK+
BCKP/WPWM
G15
BCKM/OPT_P RXACK-
G17
B3P/OPT_N RXA3+
G16
RXA3-
B3M/FLK
H16
B4P/GCLK6 RXA4+
H17
B4M/GLCK5 RXA4-
H15
C0P/LV0+ RXC0+
J15
RXC0-
C0M/LV0-
J17
C1P/LV1+ RXC1+
J16
C1M/LV1- RXC1-
K16
RXC2+
C2P/LV2+
K17
C2M/LV2- RXC2-
K15
CCKP/LV3+ RXCCK+
L15
CCKM/LV3- RXCCK-
L17
C3P/LV4+ RXC3+
L16
RXC3-
C3M/LV4-
M16
C4P/LV5+ RXC4+
M17
C4M/LV5- RXC4-
M15
D0P/LV6+ RXD0+
N15
D0M/LV6- RXD0-
N17
RXD1+
D1P/LV7+
N16
D1M/LV7- RXD1-
P15
RXD2+
D2P/LV8+
R15
D2M/LV8- RXD2-
R17
DCKP/GOE RXDCK+
R16
RXDCK-
DCKM/GSC/GCLK3
T16
D3P/GSP_R RXD3+
T17
D3M/GSP RXD3-
T15
RXD4+
D4P/SOE
U17
D4M/POL RXD4-
P16
GCLK4 GCLK4
P17
GCLK2 GCLK2
D1
I2CS_SDA URSA3_SDA
D2
I2CS_SCL
URSA3_SCL
P14
PWM0 FRC_PWM0
R14
FRC_PWM1
PWM1
B13
V_SYNC
LPLL_FBCLK
U16 R9043 0
LPLL_OUTCLK OPT
A13
LPLL_REFIN
+3.3V_MEMC
R9040
0
FRC_CONF0
FRC_CONF1
FRC_PWM1
FRC_PWM0
FRC_PWM1
FRC_PWM0
I2C ADR: GPIO1: HI:B8 LOW:B4
CHIP_CONF: {GPIO8, PWM1, PWM0}
CHIP_CONF= 3 d5: boot from internal SRAM
CHIP_CONF= 3 d6: boot from EEPROM
CHIP_CONF= 3 d7: boot from SPI Flash
COMMON 2009.09.11
URSA3 (NO L.D.) 90