Operation - Novatech 409B Instruction Manual

Fn 4.4209530
where 'n' is your selected channel
You must account for your clock frequency error and
calculation roundoff when using an external clock.
Some hand calculators may not have enough digits
to match the resolution of the 409B. See Appendix B
if your unit has the /R option installed.
4.11 Beginning with Software Revision 2.1, it is
possible to control the internal range bit on the DDS
ASIC.
4.12 For normal operation the Kp command is
unmodified. However, if it is desired that the clock
multiplier gain bit be set HIGH (for Kp*[Ext Clk
Freq] from 255 and 500 MHz), add hexadecimal
0x80 to the Kp value to be set. For the bit to be
forced LOW (100 to 160 MHz), add hexadecimal
0x40 to the Kp value to be set.
4.13 Since the resolution of the 409B is 32-bits, the
typical fractional frequency error (∆f/f) for output
frequencies in the MHz range will be less than
0.1ppm, even when exact values are not possible.
Typical ∆f/f for External Clock of 10.0MHz
Desired
Kp Fout
15 1.544MHz
Fn 4.4209530
20 1.544MHz
Fn 3.3157148
15 2.048MHz
Fn 5.8640620
20 2.048MHz
Fn 4.3980465
The "B" command can be used to test AD9959 DDS
chip programming as it allows access to all internal
registers. While not a real-time simulation, each
"B" command functions as an input by putting a
data byte directly into the AD9959 via an SPI port,
and then pulses the IOUD line. This is the similar to
a procedure that a customer control circuit might
perform. Consult the Analog Devices AD9959 data
sheet for detailed information.
NOVATECH INSTRUMENTS
NOTE:
Command
2.19x10
1.43x10
1.45x10
2.02x10
NOTE:
4.14 Phase relationships are maintained by appro-
priate use of the "M" and "I" commands. The "M"
command has special modes "M a" and "M n".
"M a" means automatically clear phase at the end
of each command. This will clear the phase register
each time any command is performed. This is
important when all outputs must be phase aligned.
However, it will cause a phase jump in the output.
4.15 The "M n" command turns off the automatic
clearing of the phase register. This is the default
mode. In this mode, the phase register is left intact
when a command is performed. Use this mode if you
want frequency changes to remain phase synchro-
nous, with no phase discontinuities.
4.16 Further control of phase relationships and tim-
ing of command execution can be exercised by
using the "I m", "I a" and "I p" commands.
The default mode is "I a" in which a command is
parsed and executed immediately following the end
of the serial input sequence. In the "I m" mode, an
update pulse will not be sent to the DDS chip until
an "I p" command is sent. This is useful when it is
important to change all the outputs to new values
simultaneously.
4.17 For applications which require precise ampli-
tude matching between the channels, the recom-
mended method is to use the "Vn N" command to
∆f/f
adjust the channels to match the other. This com-
mand provides 10-bits of adjustment range.
-8
-8
5.0
-8
5.1 Please refer to the simplified System Block Dia-
-8
gram in Figure 3 for the following discussion.
5.2 At every cycle of the 409B master clock, the 32-
bit DDS integrated circuit increments the phase of
an internal register by a value determined by the fre-
quency setting loaded into the on-chip registers.
This digital phase value is converted on-chip to a
sinusoidal amplitude level and delivered to on-chip
10-bit digital-to-analog converters. The analog sig-
nals from these converters are filtered by differential
7th-order elliptical low pass filters, amplified and
sent to the BNC receptacles.
6
Theory of Operation
409B Manual, 17-Apr-2015