1. CONTROLS AND CONNECTIONS TX/BUSY HX290 DIAL Figure 1-1 u u LAMP key (power / volume) knob i i SCN (scan) key w w CH (channel) knob o o DIAL key e e TX/BUSY Indicator ! ! 0 0 T/A (Talkaround) key r r Antenna connector ! ! 1 1 H/L (high/low) key t t PTT switch...
2. THEORY OF OPERATIONS Note : Refer to the block diagrams (figure 2-1 through 2-8) in the text for the operations of the circuits. 2.1 PLL Block The PLL block comprises a VCO, TCXO, PLL IC, and PLL loop filter. The VCO circuit generates the transmission signal and first local signal directly.
2.1.6 VCO Circuit level output. This high level output signal is input to an The DC voltage output by the PLL loop filter is input to a unlock switch QP04, causing it to turn on. When the variable capacitance diode built into the VCO. This DC unlock switch is on, a low level output signal is input to pin voltage changes the capacitance between the electrodes 37 of microprocessor QL02.
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2.2.4 Second IF Circuit The second IF IC comprises a second local oscillator, the first IF signal is converted into a 455 kHz second IF second mixer, second IF amplifier, wave detector, noise signal. After having adjacent signal elements eliminated amplifier, and noise wave detector.
2.2.6 Squelch Circuit 2.2.7 Tone Decoder A portion of the audio signal output from pin 9 of second A portion of the audio signal output from pin 9 of second IF IC QH04 is input to a band-pass filter consisting of IF IC QH04 is input to tone detector circuit built into base CH23, RH22,CH30,RH14, CH21, CH22, RH12 and band IC QM01 as the tone signal.
2.4 Control Block 2.4.1 Microprocessor QL02 The functions of the In / Out ports of microprocessor QL02 are listed below. Table 2-1 Port Name S.I/O S.PD Signal Name In/Out Active Initial P.UP/DN Function SEG05 SEG05 LCD segment output SEG06 SEG06 LCD segment output SEG07 SEG07...
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Port Name S.I/O S.PD Signal Name In/Out Active Initial P.UP/DN Function RSTX RESET (High) E-UP Reset input N.C. Sub clock connection terminal (N.C.) N.C. Sub clock connection (N.C.) MODA Operation mode specified (Vss) Main clock connection (9.8304 MHz) Main clock connection (9.8304 MHz) P80/INT24 CMOS CLK SHIFT...
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2.4.2 Display (LCD) Microprocessor QL02 drives LCD QL01 directly. The driving method is dynamic drive using 24 segment terminals, two common terminals, and a 1/3 duty ratio. The LCD segment and common connections are illustrated below.(Figure2-7) SEGMENT COMMON Figure 2-7 LCD connection diagram...
3. DISASSEMBLY Note : Be sure to switch off the transceiver's power before disassembling it. And then remove an antenna and a battery pack. 3.1 Removing the Diecast frame (d) Pull the diecast frame up from front case in the (a) Remove the single screw A to remove the Mic/Spk direction indicated by arrow q, and remove the it in jack cover.
3.2 Removing the TX/RX/CONTROL P.C.board (d) Remove the two screws E to remove the switching (a) Remove the frame packing. (b) Remove the two nuts D. plate and two clampers. (c) Remove the solder from area e on the TX/RX/CONTROL (e) Remove the three screws F.
4. ADJUSTMENT Make sure that all test equipment is properly calibrated. Allow sufficient time after powering on equipment for it to warm up before performing adjustments. - Standard conditions - Power supply voltage ............................DC 7.2 V Audio output ................................200 mW Audio load ..................................8 Ω...
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(b) Turn on the power switch while holding down the DIAL key and LAMP key at the same time. At this point, the "Adj XX" (XX : channel number) indication on the LCD of the transceiver. - For the HX290UKA - Turn on the power switch while holding down the DIAL key and LAMP key at the same time.
4.1 Adjustment Connection Diagrams Frequency Counter Deviation & Audio Generator AC Voltmeter Power Meter Directional Coupler RF Dummy Load (50 ohm) Oscilloscope Power Supply CAUTION : Use a microphone plug of the type shown below when adjusting the transmitter block. 10µF / 10V Microphone plug DC +7.2V...
4.3 HX290UKA Adjustment and Confirmation (f) At this point, adjust RM52 so that the waveform is a 4.3.1 PLL Block square wave. - Reception PLL lock voltage adjustment - (g) When the adjustment is complete, power off the (a) Set the transceiver channel to 02 and set the transceiver.
(j) At this point, confirm that the CTCSS deviation is 4.3.3 Receiver Block between ± 0.35 kHz and ± 0.6 kHz - Reception sensitivity confirmation - (k) At this point, confirm that the TX frequency is between (a) Set the transceiver channel to 01. + 1 kHz and - 1 kHz.
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- Squelch sensitivity confirmation - (e) Input a 1 kHz, 1 Vp-p audio signal to pin 5 or 6 of JL04 (a) Press the MONI key twice within 1 second to set the from the audio generator. (AC connection by 0.1 µF) squelch level.
5. SPECIFICATIONS Frequency range F1...............................405MHz to 430 MHz F3..............................450 MHz to 470 MHz F9..............................370 MHz to 390 MHz F8..............................345 MHz to 370 MHz Number of channels..........................Max 100 channels Channel separation Wide ..................................25 kHz Narrow ..................................12.5 kHz Operation voltage range ..........................6.0 to 9.0 VDC Operation temperature range........................–...
6. PARTS LIST Parts list The parts list contains information on electrical and mechanical parts. Electrical parts are listed first, followed by mechanical parts. Chip parts Part numbers whose first three characters correspond to the following codes indicate chip parts. -Capacitors- -Resistors- -Semiconductors-...
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Ref. Ref. Q'TY Part No. Description Desig. Q'TY Part No. Description Desig. MECHANISM MECHANISM 001B 408B064010 FRONT CASE 111B 408B107040 CU SHEET FOR DIE CAST FRAME 002B 408B270010 PTT BUTTON 112B 408B002020 SIDE CLAMPER (ANT SIDE) 003B 408B118010 SPACER FOR PTT BUTTON 113B 408B002030 SIDE CLAMPER (LAMP KEY SIDE)
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