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offending
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CIRCUIT
DESCRIPTION
(WITH
TROUBLESHOOTING
HINTS):
General
The
418
is
divided
into four
major blocks.
In
order of
signal
passage these
are:
1)
The
input buffer
and broadband
AGC;
2)
The
program-controlled pre-emphasis,
which
serves
as a
high-frequency
limiter;
3)
The
de -emphasis
and
output
stage;
and
4)
The power
supply.
Left
and
right
audio
paths are identical,
and
share a
common
control circuit.
Only
the
left
channel,
plus
the
control
circuit will
be
described.
Input
Buffer
and Broadband
AGC:
The
signal enters the
41
8A
in
balanced
form,
and
is
applied
to
IC201, an LF356 low-noise FET-input
opamp
configured
as a
gain-of-one
differential
amplifier.
When
both
(+)
and
(-)
inputs
are driven from source
impedances
very
small
compared
to
50K
(such as
600
ohms), the
am-
plifier
is
essentially insensitive to signal
components
that
appear
equally on both
(+)
and
(-)
inputs (such as
hum),
and
responds with
full
unity
gain to the difference bet-
ween
the
(+)
and
(-)
input.
Thus
it
serves
as
an
"active
transformer.
If
signals
in
excess of +21
dBm
are
applied
to the input,
this
amplifier
will
clip regardless of the setting of the in-
put attenuator,
and an
external
balanced
loss
pad must be
employed
before the
41
8A
input.
The
gain
control
element
is
a
P-channel
junction
field
effect
transistor,
IC2I6A, operated
as a
voltage variable
resistor.
This
FET
shunts
the lower
leg of
the
voltage di-
vider R213,
223
to
reduce
the gain.
Note
that the
va-
lues of
R213
and R223
are selected
at
the factory to
com-
plement
the particular
FET
employed.
If
IC216
is
ever
replaced
(a
highly unlikely occurrence), the factory
should be consulted.
The audio
level
across
the FET
is
16
mv
at
the thresh-
old
of limiting.
This level
is
amplified
back
up by IC205,
a
709
opamp
configured
for
34.5
dB non-inverting gain.
IC205
is
frequency-compensated by C2I3,
217, 219
and
R215, 217.
The
output
of
IC205
is
clamped
to
+2.4
volts
by the diode
strings
CR20I, 203, 205, 207, 209,
211, 213, 215
to
prevent
damage
to 1C
207
in
the event
that
excessive
input signal
is
applied.
The
gain
of
IC205
is
determined by R219, 221, and
C225. R229
forces a
constant current
to
flow from the output
of
IC205
to the
-15
supply,
thus forcing the
output stage
of
IC205
to
operate
class
A
to
eliminate
crossover distortion.
The
output
of
IC205
is
applied
to
the
two
halves
of
IC207,
a 711 dual
comparator.
The
inputs of
IC207
also
receive reference voltages
of
+and
-1
.2 volts
derived
from voltage
dividers
R294-297.
If
the
peak
level of
the output
of'
IC205
attempts
to
exceed
+1
.2
volts,
1C
20 7
turns
on,
producing
a pulse
which
is
coupled
through
C266
and
CR228
to
Q21
1
.
Q21
1
is
turned on
by
the
pulse,
and
discharges
C267
and
C268
through
CR230
and
CR229
respectively.
This
voltage
change
across
C267
is
coupled
to
the gate of the
FET through
R231
,
thereby decreasing the
resistance of the
FET and
decreasing
the gain of the
circuit
until
the
overload
at
the output of
IC205
is
removed. Attack
time
of
the
cir-
cuit
is
determined by R288
and
is
about
2 ms.
The
re-
lease
time
is
a very
complex
function of the nature of
the
program,
and
is
determined by
the proprietary
cir-
cuit inside
the
module.
Basically, the
module
derives
a voltage
based on
the previous
history of
the
program
and
applies the voltage to
one end
of
the
RELEASE TIME
control,
P211.
The
other
end
of
P211
is
connected
to
C268,
and
permits
C268
to
charge
at
a
rate
controlled
by
the
module
in
conjunction with the
setting
of
P211.
In
addition, the
network
CR231 and R289
provides
de-
layed
release
to
assure
low
distortion at
low frequencies.
This
is
accomplished
as follows:
When
gain reduction occurs, both
C267
and
C268
are
discharged
to the
same
voltage
because
CR230 and CR229
have
substantially identical
voltage
drops.
However,
C267
must charge
(release)
through
CR231 and R289.
R289
provides
virtually
no
short-term release
because
of
its
high value.
Therefore,
C267
cannot charge
until
C268
has
charged
sufficiently to
overcome
the turn-on
voltage
of
CR231
.
This
time delay
eliminates the
usual
sawtooth
ripple
on the
control
voltage,
thus drastically
reducing
distortion.
The
collector
of
Q211
is
clamped
to
ground through
the base-emitter junction of
Q210.
This
way,
the gate
of the control
FET cannot be forward-biased.
In
addi-
tion,
when
Q210
conducts,
it
turns
on
the
front
-panel
OVERLOAD
LED,
thus indicating that
the permissable
15
dB
gain reduction
range
has
been exceeded.
P210 determines
the quiescent gate voltage of the
control
FET,
and
is
adjusted
to
pinch
this
FET
off
when
no
gain reduction occurs.
Thus
maximum
gain
is
extre-
mely
stable,
and
no
distortion
is
introduced
by
the FET.
The
control
FET
is
contained
in
a
package
with
four
matched,
monolithic
FET's.
The second
FET
is
used
to
control the
gain of the
right
channel;
the
third
FET
is
operated with
DC
across
it
to control
the
GAIN
REDUC-
TION
meter.
The
fourth
FET
is
not used.
The
DC
gain
reduction
signal
is
amplified
by IC219,
a
non-inverting
opamp
5
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