Dell GCR-8481B Service Manual page 22

Pin No. Symbol
153 HDBA
154 HDB5
155 VSIO7
156 HDB9
157 HDB6
158 HDB8
159 HDB7
160 VDC5
161 XTL2
162 XTL1
163 VSC5
164 MTST0
165 AVS3
166 PWM2N
167 PWM2P
168 AVD3
169 AVD4
170 XTLO
171 XTLI
172 AVS4
173 AVS5
174 PWM1P
175 PWM1N
176 AVD5
Notes :
• LRCK, BCK and PCMD are changed to 32-bit slot and 48-bit slot by command.
32-bit slot is output in 2's complements on an LSB-first basis and 48-bit slot is output in 2's complements on
an MSB-first basis.
• *'s signal is able to convert to output by a command. (Refer to sub CPU Register 08h (W) of decoder part)
• The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.
• XRAOF is a signal issued when a jitter margin of +28F is exceeded by the 32K RAM.
• C2PO is a signal to indicate data error.
• XUGF is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected.
• GTOP monitors the state of Frame Sync protection. ("H" : Sync protection window released)
• XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
coincides with a change point of the EFM signal.
• RFCK is a signal generated at 136-µs periods using a crystal oscillator.
• LOCK is sampling the GFS at 460Hz and outputs "H" when GFS is "H".
("L" outputs when "L" is output eight times in succession or inputs when LKIN is "H".)
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I/O
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
Digital Power Supply GND
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
Digital Power Supply (2.5V)
O 1, 0 Crystal Oscillating Circuit Output of the Clock for Decoder
I Crystal Oscillating Circuit Input of the Clock for Decoder
Digital GND
I Test Pin. Normally "L"
Analog GND
O 1, 0 PWM Output of Audio DAC. Default R Ch, Reverse Phase
O 1, 0 PWM Output of Audio DAC. Default R Ch, Forward Phase
Analog Power Supply (2.5V)
DSP, Power Supply for Audio DAC Clock (2.5V)
O 1,0 DSP, Crystal Oscillating Circuit Output for the Audio DAC Clock
I DSP, Crystal Oscillating Circuit Input for the Audio DAC Clock
DSP, GND for the Audio DAC Clock
Analog GND
O 1, 0 PWM Output of Audio DAC. L Ch, Forward Phase
O 1, 0 PWM Output of Audio DAC. L Ch, Reverse Phase
Analog Power Supply (2.5V)
COMMENT