Philips 50pf9966 Service Manual page 119

EN 122 9. FTP2.2U AA
9.15.11 Diagram B14F, SiI9993CT100 (IC7I18)
BLOCK DIAGRAM
RESET#
I 2 C
DSDA
Slave
DSCL
HDCP
Keys
EEPROM
R_EXT
RXC±
PanelLink
TMDS
RX0±
Digital
RX1±
Core
RX2±
PIN CONFIGURATION
Q13
Q12
Q11
Q10
Q9
OVCC
OGND
Q8
Q7
Q6
Q5
Q4
Q3
VCC
GND
OGND
OVCC
Q2
Q1
Q0
INT
RESET#
RSVDL
CSCL
CSDA
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Registers
----------------
Configuration
Logic Block
HDCP
Decryption
Engine
Mode
XOR
Mask
Control
TM
control
signals
control
signals
51
52
53
54
55
56
57
58
59
60
61 SiI 9993
62
100-Pin
63
64
TQFP
65
66
(Top View)
67
68
69
70
71
72
73
74
75
Figure 9-22 Internal block diagram and pin configuration
2
I C
Slave
Aux Data
Logic
Block
MCLK
Gen
Audio
Data
Decode
Logic
Block
Video
Color
Space
Converter
24
Up/Down
Sampling
Video
30
DAC
25 N/C
PLLIN
24
PVCC2
23
22 PGND2
21 OVCC
20 RSVDO
19 RSVDO
18 RSVDL
17 VCC
16 GND
15 AnBPb
14 DACVCCB
13 DACGNDB
12 AnGY
11 DACVCCG
10 DACGNDG
9 RSET
8 COMP
7 AnRPr
6 DACVCCR
5 DACGNDR
4 N/C
3 N/C
2 DACGND
1 DACVCC
CSDA
CSCL
MCLKOUT
MCLKIN
SCK
WS
SD0
SPDIF
DE
HSYNC
VSYNC
ODCK
Q[23:0]
AnGY
AnRPr
AnBPb
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