Aiwa CSD-ED79 Service Manual page 19

IC, LC78622ED
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Pin Name I/O
DEFI I Defect detection signal (DEF) input terminal.
TAI I A pull-down resistor is built in. (Connected to 0V)
PDO O External VCO control phase comparator output.
VVSS – Connected to internal VCO of PLL. (Connected to 0V)
ISET I PDO output current adjustment resistor connection.
VVDD – Voltage terminal for internal VCO of PLL.
FR I VCO frequency range adjustment.
VSS – Digital system ground. (Connected to 0V)
EFMO O EFM signal output pin.
EFMIN I EFM signal input pin.
T2 I Test pin. (Connected to 0V)
CLV+
O Disc motor control output.
CLV–
Rough servo/phase control automatic switching monitor output.
V/P O
Rough servo at "H". Phase control at "L".
HFL I Track detection signal input.
TES I Tracking error signal input.
TOFF O Tracking off output.
TGL O Tracking gain switching output.
JP+
O Track jump output.
JP–
PCK O EFM data playback monitor. Outputs 4.3218MHz when the phase is locked. (Not used)
Synchronization signal detection output. Outputs a "H" level when the synchronization
FSEQ O signal detected from EFM signal and internally generated synchronization signal
range.(Not used)
VDD – Digital system power supply.
SL+
O Serial data command sled signal output terminal from microprocessor.
SL–
NC – Not used.
PU IN I CD pickup inside limit switch. (Not used)
NC – Not used.
De-emphasis monitor pin. A "H" level indicates playback of a de-emphasis disc.
EMPH O
(Not used)
C2F O C2 flag output. (Not used)
DOUT O Digital output (EIAJ format). (Not used)
T3 I Test input. (Connected to 0V)
T4 I Test input. (Connected to 0V)
NC – Not used.
MUTEL O Left channel mute output. (Not used)
x ao
y
LVDD – Left channel power supply.
i
LCHO O Left channel output.
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