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Atlantis COM-870E User Manual

Wide range temperature com express type 6 cpu module
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85
COM-870E
Wide Range Temperature
COM Express Type 6 CPU Module
User's Manual
Version 1.0
85
2012.06

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Summary of Contents for Atlantis COM-870E

  • Page 1 COM-870E Wide Range Temperature COM Express Type 6 CPU Module User’s Manual Version 1.0 2012.06...
  • Page 2 This page is intentionally left blank.

  • Page 3: Table Of Contents

    Index Contents Chapter 1 - Introduction ..............1 1.1 Copyright Notice ................2 1.2 Declaration of Conformity ............2 1.3 About This User’s Manual ............4 1.4 Warning ..................4 1.5 Replacing the Lithium Battery.............4 1.6 Technical Support ................4 1.7 Warranty ..................5 1.8 Packing List ..................6 1.9 Ordering Information ..............6 1.10 Specifications ................7 1.11 Board Dimensions ..............8...
  • Page 4 Index 3.3 Chipset ..................34 3.3.1 System Agent (SA) Configuration ........35 3.3.2 PCH-IO Configuration ............45 3.4 Boot Settings ................50 3.5 Security ..................51 3.6 Save & Exit ..................53 3.7 AMI BIOS Checkpoints ...............54 3.7.1 Checkpoint Ranges ............54 3.7.2 Standard Checkpoints ...........55 Appendix ....................63 Appendix A: I/O Port Address Map ..........64 Appendix B: Interrupt Request Lines (IRQ) ........67 Appendix C: BIOS Memory Map ............68...

  • Page 5: Chapter 1 Introduction

    Introduction Chapter 1 Introduction Chapter 1 - Introduction - 1 -...

  • Page 6: Copyright Notice

    Introduction 1.1 Copyright Notice All Rights Reserved. The information in this document is subject to change without prior notice in order to improve the reliability, design and function. It does not represent a commitment on the part of the manufacturer. Under no circumstances will the manufacturer be liable for any direct, indirect, special, incidental, or consequential damages arising from the use or inability to use the product or documentation, even if advised of the possibility of such...
  • Page 7 Introduction (1)This device may not cause harmful interference, and (2)This device must accept any interference received, including interference that may cause undesired operation. NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment.

  • Page 8: About This User's Manual

    Introduction 1.3 About This User’s Manual This user’s manual provides general information and installation instructions about the product. This User’s Manual is intended for experienced users and integrators with hardware knowledge of personal computers. If you are not sure about any description in this booklet. please consult your vendor before further handling.

  • Page 9: Warranty

    Introduction 1.7 Warranty This product is warranted to be in good working order for a period of two years from the date of purchase. Should this product fail to be in good working order at any time during this period, we will, at our option, replace or repair it at no additional charge except as set forth in the following terms.

  • Page 10: Packing List

    Packing List Before you begin installing your single board, please make sure that the following materials have been shipped: 1 x COM-870E COM Express CPU Module 1 x Driver CD 1 x Quick Installation Guide If any of the above items is damaged or missing, contact your vendor immediately.

  • Page 11: Specifications

    Introduction 1.10 Specifications COM Express Type 6 CPU Module Form Factor Intel ® Celeron™ 827E 1.4GHz processor Intel ® HM65 Chipset 2 x DDR3 SO-DIMM sockets, supporting up to 8GB System Memory SDRAM Intel ® Graphics Media Accelerator 3000 graphics VGA/ LCD core w/ Analog RGB/ Dual Channels 24-bit LVDS Controller...

  • Page 12: Board Dimensions

    Introduction 1.11 Board Dimensions 71,58 30,00 4,00 Sandy Bridge Processor QM67 76,00 41,00 4,00 55,68 86,01 125,00 45,35 Ø2.6*Ø6.5 Unit: mm - 8 -...

  • Page 13: Chapter 2 Installation

    Installation Chapter 2 Installation Chapter 2 - Installation - 9 -...

  • Page 14: What Is "Com Express

    Installation 2.1 What is “COM Express”? With more and more demands on small and embedded industrial boards, a multi-functioned COM (Computer-on-Module) is the great one of the solutions. COM Express, board-to-board connectors consist of two rows of 220 pins each. Row AB, which is required, provides pins for PCI Express, SATA, LVDS, LCD channel, LPC bus, system and power management, VGA, LAN, and power and ground interfaces.
  • Page 15 Module Type 2, 3, 4, 5 and 6 support two connectors with four rows of pins (440 pins) Connector placement and most mounting holes have transparency between Form Factors. The differences among the Module Type 6 and COM-870E are summarized in table below: Module Type...

  • Page 16: Block Diagram

    Installation 2.2 Block Diagram Soldered onboard PCIex16 (PEG) Intel® DDR3-1333/1066MHz 2 x SO-DIMM DDR3 Celeron 827E sockets Processor DMI2 (x4) Dual Channels 24-bit LVDS DDI1 (DisplayPoer/HDMI/DIV/SDVO) Analog RGB HD Audio Link SATA0, 1 (600Gb/s) Intel® SATA2, 3 (300Gb/s) HM65 DDI2 (DisplayPort/HDMI/DVI) USB Port 0 ~7 5 x PCIex1 Intel 82579LM...

  • Page 17: Connectors

    Installation 2.3 Connectors Top side Sandy Bridge Processor QM67 Bottom side COM Express AB Connector COM Express CD Connector COM Express CD Connector COM Express AB Connector - 13 -...

  • Page 18: Com Express Ab Connector (Bottom Side)

    Installation 2.4 COM Express AB Connector (bottom side) GND (FIXED) GND (FIXED) PCIE_RX4- PCIE_TX4- GBE0_ACT# GBE0_MDI3- GPO2 GBE0_MDI3+ LPC_FRAME# PCIE_RX3+ PCIE_TX3+ LPC_AD0 GBE0_LINK100# PCIE_RX3- PCIE_TX3- LPC_AD1 GBE0_LINK1000# GBE0_MDI2- LPC_AD2 PCIE_RX2+ PCIE_TX2+ LPC_AD3 GBE0_MDI2+ PCIE_TX2- PCIE_RX2- LPC_DRQ0# GBE0_LINK# GPO3 GPI1 GBE0_MDI1- LPC_DRQ1# PCIE_RX1+ PCIE_TX1+...

  • Page 19: Com Express Cd Connector (Bottom Side)

    Installation 2.5 COM Express CD Connector (bottom side) GND (FIXED) GND (FIXED) PEG_TX1- PEG_RX1- TYPE2# TYPE1# USB_SSTX0- USB_SSRX0- PEG_TX2+ PEG_RX2+ USB_SSTX0+ USB_SSRX0+ PEG_TX2- PEG_RX2- GND (FIXED) GND (FIXED) USB_SSTX1- USB_SSRX1- PEG_TX3+ PEG_RX3+ USB_SSRX1+ PEG_RX3- USB_SSTX1+ PEG_TX3- RSVD RSVD USB_SSTX2- USB_SSRX2- RSVD RSVD USB_SSRX2+...

  • Page 20: The Installation Paths Of Cd Driver

    Installation 2.6 The Installation Paths of CD Driver Windows 2000 & XP Driver Path CHIPSET \EmETXe-i67M2\CHIPSET \EmETXe-i67M2\ETHERNET\XP_WIN7_SERIES\32 \EmETXe-i67M2\ETHERNET\XP_WIN7_SERIES\64 NET Framework \EmETXe-i67M2\NET Framework \EmETXe-i67M2\GRAPHICS\Windows XP 32bit Graphics Drivers\Windows XP Graphics Drivers\ winxp \EmETXe-i67M2\GRAPHICS\Windows XP 64bit Graphics Drivers\Windows XP64 Graphics Drivers\ winxp64 Management \EmETXe-i67M2\ME Engine...

  • Page 21: Heatsink Installation

    Installation 2.7 Heatsink Installation 1. Prepare your optional heatsink, thermal pad and CPU module. 2. You have to put an additional thermal pad between heatsink and CPU module. Please tear protective membranes on both sides from thermal pad first of all, be sure not to pinch or mold the thermal pad, and then put it as right picture.
  • Page 22 Installation 4. After everything is settled down, please assemble heatsink with CPU module according to their corresponding screw positions. 5. Carefully turn them over together and secure the first 3 screws as left picture. Overturn again to secure the rest as right picture. - 18 -...

  • Page 23: Chapter 3 - Bios

    BIOS Chapter 3 BIOS Chapter 3 - BIOS - 19 -...

  • Page 24: Bios Main Setup

    BIOS 3.1 BIOS Main Setup The AMI BIOS provides a setup utility program for specifying the system configurations and settings which are stored in the BIOS ROM of the system. When you turn on the computer, the AMI BIOS is immediately activated. After you have entered the setup utility, use the left/right arrow keys to highlight a particular configuration screen from the top menu bar or use the down arrow key to access and configure the information below.

  • Page 25: Advanced Settings

    BIOS System Date Set the system date. Note that the ‘Day’ automatically changes when you set the date. The date format is: Day : Sun to Sat Month : 1 to 12 Date : 1 to 31 Year : 1999 to 2099 System Time Set the system time.

  • Page 26: Acpi Configuration

    BIOS 3.2.1 ACPI Configuration Enable Hibernation Enable or disable System ability to Hibernation (OS/S4 Sleep State). This op- tion may be not effective with some OS. ACPI Sleep State Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.

  • Page 27: Cpu Configuration

    BIOS 3.2.2 CPU Configuration The CPU Configuration setup screen varies depending on the installed processor. Hyper-threading This item is used to enable or disable the processor’s Hyper-threading feature. Enabled for Windows XP and Linux (OS optimized for Hyper-threading Technology) and disabled for other OS (OS not optimized for Hyper-threading Technology).

  • Page 28: Sata Configuration

    BIOS 3.2.3 SATA Configuration It allows you to select the operation mode for SATA controller. SATA Controller(s) Enable or disable SATA devices. SATA Mode Selection The choice: Disable; IDE (Default), RAID IDE: Set the Serial ATA drives as Parallel ATA storage devices. RAID: Create RAID or Intel Matrix Storage configuration on Serial ATA devices.

  • Page 29: Intel Anti-Theft Technology Configuration

    BIOS 3.2.4 Intel Anti-Theft Technology Configuration Intel Anti-Theft Technology Enable or disable Intel® Anti-Theft Technology function in BIOS. Intel Anti-Theft Technology Recovery Set the number of times Recovery attempted will be allowed. Enter Intel AT Suspend Mode Enable or disable the request that platform enters AT suspend mode. - 25 -...

  • Page 30: Amt Configuration

    BIOS 3.2.5 AMT Configuration BIOS Hotkey Pressed OEMFLag Bit 1: Enable/Disable BIOS hotkey press. MeBx Selection Screen OEMFLag Bit 2: Enable/Disable MEBx selection screen. Verbose Mebx Output OEMFLag Bit 3: Enable/Disable Verbose Mebx Output. - 26 -...
  • Page 31 BIOS Hide Un-Configure ME Confirmation OEMFLag Bit 6: Hide Un-Configure ME without password Confirmation Prompt. MeBx Debug Message Output OEMFLag Bit 14: Enable MEBx debug message output. Un-Configure ME OEMFLag Bit 15: Un-Configure ME without password. Intel AMT Password Write Enabled Enable/Disable Intel AMT Password Write.

  • Page 32: Usb Configuration

    BIOS 3.2.6 USB Configuration Legacy USB Support Enable support for legacy USB. AUTO option disables legacy support if no USB devices are connected. The choice: Enabled (Default); Auto; Disabled EHCI Hand-off Allow you to enable support for operating systems without an EHCI hand-off feature.

  • Page 33: H/W Monitor

    BIOS USB hardware delays and time-outs USB transfer time-out — The time-out value for control, bulk, and interrupt transfers. Default setting: 20 sec Device reset time-out — USB mass storage device start unit command time- out. Default setting: 20 sec Device power-up delay —...

  • Page 34: Super Io Configuration

    BIOS 3.2.8 Super IO Configuration You can use this item to set up or change the Super IO configuration for FDD controllers, parallel ports and serial ports. Power On After Power Failure Specify what state to go to when power is re-applied after a power failure. - 30 -...

  • Page 35: Serial Port

    BIOS Serial Port 1~2 Configuration Serial Port Use the Serial port option to enable or disable the serial port. The choice: Enabled, Disabled Change Settings Use the Change Settings option to change the serial port’s IO port address and interrupt address. The choice: Auto IO=3F8h;...
  • Page 36 BIOS Parallel Port Configuration Parallel Port Configuration This item allows you to enable/disable Parallel Port (LPT/LPTE). Change Settings Use the Change Settings option to change the parallel port’s IO port address and interrupt address. The choice: Auto IO=378h; IRQ=5, IO=378h; IRO=5,6,7,10,11,12, IO=378h;...

  • Page 37: Sandybridge Ppm Configuration

    BIOS 3.2.9 Sandybridge PPM Configuration EIST Enable/Disable Intel SpeedStep. CPU C3 Report Enable/Disable CPU C3(ACPI C2) report to OS. CPU C6 Report Enable/Disable CPU C6(ACPI C3) report to OS. CPU C7 Report Enable/Disable CPU C7(ACPI C3) report to OS. Long duration power limit Long duration power limit in Watts, 0 means use factory default.

  • Page 38: Chipset

    BIOS 3.3 Chipset This section allows you to configure and improve your system; also, set up some system features according to your preference. - 34 -...

  • Page 39: System Agent (Sa) Configuration

    BIOS 3.3.1 System Agent (SA) Configuration CHAP Device (B0:D7:F0) Enable or disable SA CHAP Device. Thermal Device (B0:D4 F0) Enable or disable SA Thermal Device. Enable NB CRID Enable or disable NB CRID WorkAround. - 35 -...

  • Page 40: Graphics Configuration

    BIOS Graphics Configuration Primary Display Select which of IGFX/PEG/PCI Graphics Devices should be Primary Display or select SG for Switchable Gfx. Internal Graphics Keep IGD enabled based on the option. GTT Size Select the GTT Size: 1MB, 2MB. Aperture Size Select the Aperture Size: 128MB, 256MB, 512MB.

  • Page 41: Lcd Control

    BIOS Gfx Low Power Mode This option is applicable for SFF only. LCD Control Primary IGFX Boot Display Select the Video Device which will be activated during POST. This has no ef- fect if external graphics present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display.

  • Page 42: Backlight Control

    BIOS Backlight Control The choice: PWM Inverted (Default), PWM Normal, GMBus Inverted and GM- Bus Normal. The choice: VBIOS Default, Disabled and Level 1/2/3/4/5. Spread Spectrum clock Chip The default setting is Off. Other options are: Hardware: Spread is controlled by chip. Software: Spread is controlled by BIOS.
  • Page 43 BIOS DMI Configuration Control various DMI functions. DMI Vc1/Vcp/Vcm Control Enable or disable DMI Vc1/Vcp/Vcm. DMI Link ASPM Control Enable or disable the control of Active State Power Management on SA side of the DMI Link. The choice: Disabled, L0s, L1, L0sL1 DMI Extended Synch Control Enable or disable DMI Extended Synchronization.

  • Page 44: Nb Pcie Configuration

    BIOS NB PCIe Configuration Configure NB PCIe Express Settings. PEG0 – Gen X Configure PEG0 B0:D1:F0 Gen1-Gen2. The choice: Auto, Gen1, Gen2 PEG1 – Gen X Configure PEG1 B0:D1:F1 Gen1-Gen2. The choice: Auto, Gen1, Gen2 PEG2 – Gen X Configure PEG2 B0:D1:F2 Gen1-Gen2. The choice: Auto, Gen1, Gen2 PEG3 –...

  • Page 45: Memory Configuration

    BIOS PEG ASPM Control ASPM support for the PEG Device. This has no effect if PEG is not the currently active device. The choice: Disabled, Auto, ASPM L0s, ASPM L1, ASPM L0sL1 De-emphasis Control Configure the De-emphasis control on PEG. The choice: -6 dB, -3.5 dB Memory Configuration DIMM profile...
  • Page 46 BIOS Max TOLUD Maximum Value of TOLUD. Dynamic assignment would adjust TOLUD automatically based on largest MMIO length of installed graphic control- ler. The choice: Dynamic, 1GB, 1.25 GB, 1.5 GB, 1.75 GB, 2GB, 2.25 GB, 2.5 GB, 2.75 GB, 3 GB, 3.25 GB NMode Support NMode Support Option.
  • Page 47 BIOS Memory Thermal Configuration Memory Thermal Configuration Options. Memory Thermal Management Enable or disable Memory Thermal Management. PECI Injected Temperature Enable or disable memory temperatures to be injected to the processor via PECI. EXTT# via TS-on-Board Enable or disable routing TS-on-Board’s ALERT# and THERM# to EXTTS# pins on the PCH.
  • Page 48 BIOS GT – Power Management Control RC6 (Render Standby) Check to enable render standby support. GT Overclocking Support Enable or disable GT Overclocking Support. - 44 -...

  • Page 49: Pch-Io Configuration

    BIOS 3.3.2 PCH-IO Configuration PCIE Wake UP Enable or disable PCIE Wake# to wake the system. Wake on RING Enable or disable Wake on RING (WOR). Computer will start up simply by ap- plying power to a connected external modem if WOR is enabled. Azalia Control detection of the Azalia device.
  • Page 50 BIOS USB Configuration EHCI1~2 Control the USB EHCI (USB2.0) functions. One EHCI controller must always be enabled. USB Ports Per-Port Disable Control Enable or disable each of the USB ports (0~9). - 46 -...
  • Page 51 BIOS PCI Express Configuration PCI Express Clock Gating Enable or disable PCI Express Clock Gating for each root port. DMI Link ASPM Control The control of Active State Power Management on both NB side and SB side of the DMI Link. DMI Link Extended Synch Control The control of Extended Synch on SB side of the DMI Link.
  • Page 52 BIOS PCI Express Root Port 1~8 PCI Express Root Port 1~8 Control the PCI Express Root Port. PEG1 – Gen X Configure PEG1 B0 :D1 :F1 Gen1-Gen2 The choice: Auto, Gen1, Gen2 ASPM Support Set the ASPM Level to Disabled, L0s, L1, L0sL1, Auto Force L0 - Force all links to L0 State AUTO - BIOS auto configuration DISABLE - Disable ASPM...
  • Page 53 BIOS Enable or disable PCI Express Unsupported Request Reporting. Enable or disable PCI Express Device Fatal Error Reporting. NFER Enable or disable PCI Express Device Non-Fatal Error Reporting. Enable or disable PCI Express Device Correctable Error Reporting. Enable or disable PCI Express Completion Timer TO. SEFE Enable or disable Root PCI Express System Error on Fatal Error.

  • Page 54: Boot Settings

    BIOS 3.4 Boot Settings The Boot menu items allow you to change the system boot options. Boot Configuration Bootup NumLock State This setting determines whether the Num Lock key should be activated at boot up. Quiet Boot This allows you to select the screen display when the system boots. Boot Option Priorities Select the boot sequence of the hard drives.

  • Page 55: Security

    BIOS 3.5 Security Administrator Password Use the Administrator Password to set or change a administrator password. ENTER PASSWORD Type the password, up to eight characters in length, and press <Enter>. The password typed now will clear any previously entered password from CMOS memory.
  • Page 56 BIOS changing any part of your system configuration. Additionally, when a password is enabled, you can also require the BIOS to request a password every time your system is rebooted. This would prevent unauthorized use of your computer. You can determine when the password is required within the BIOS Features Setup Menu and its Security option.

  • Page 57: Save & Exit

    BIOS 3.6 Save & Exit Save Changes and Reset Pressing <Enter> on this item and it asks for confirmation: Save configuration changes and exit setup? Pressing <OK> stores the selection made in the menus in CMOS - a special section of memory that stays on after you turn your system off. The next time you boot your computer, the BIOS configures your system according to the Setup selections stored in CMOS.

  • Page 58: Ami Bios Checkpoints

    BIOS 3.7 AMI BIOS Checkpoints 3.7.1 Checkpoint Ranges Status Code Range Description 0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors PEI execution up to and including memory 0x10 – 0x2F detection 0x30 – 0x4F PEI execution after memory detection 0x50 –...

  • Page 59: Standard Checkpoints

    BIOS 3.7.2 Standard Checkpoints SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on. Reset type detection (soft/hard). 0x02 AP initialization before microcode loading 0x03 North Bridge initialization before microcode loading 0x04 South Bridge initialization before microcode loading 0x05 OEM initialization before microcode loading 0x06...
  • Page 60 BIOS PEI Phase Status Code Description Progress Codes 0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13 Pre-memory CPU initialization (CPU module specific) 0x14 Pre-memory CPU initialization (CPU module specific) 0x15 Pre-memory North Bridge initialization is started Pre-Memory North Bridge initialization (North Bridge...
  • Page 61 BIOS 0x32 CPU post-memory initialization is started 0x33 CPU post-memory initialization. Cache initialization CPU post-memory initialization. Application Processor(s) 0x34 (AP) initialization CPU post-memory initialization. Boot Strap Processor 0x35 (BSP) selection CPU post-memory initialization. System Management 0x36 Mode (SMM) initialization 0x37 Post-Memory North Bridge initialization is started Post-Memory North Bridge initialization (North Bridge 0x38...
  • Page 62 BIOS 0x55 Memory not installed 0x56 Invalid CPU type or Speed 0x57 CPU mismatch 0x58 CPU self test failed or possible CPU cache error CPU micro-code is not found or micro-code update is 0x59 failed 0x5A Internal CPU error 0x5B reset PPI is not available 0x5C-0x5F Reserved for future AMI error codes...
  • Page 63 BIOS 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB – 0xFF Reserved for future AMI error codes DXE Phase Status Code Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64...
  • Page 64 BIOS South Bridge DXE Initialization (South Bridge module 0x74 specific) South Bridge DXE Initialization (South Bridge module 0x75 specific) South Bridge DXE Initialization (South Bridge module 0x76 specific) South Bridge DXE Initialization (South Bridge module 0x77 specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A –...
  • Page 65 BIOS 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE...
  • Page 66 BIOS 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error) 0xDB Flash update is failed 0xDC Reset protocol is not available ACPI/ASL Checkpoints Status Code Description 0x01...

  • Page 67: Appendix

    Appendix Appendix Appendix - 63 -...

  • Page 68: Appendix A: I/O Port Address Map

    Appendix Appendix A: I/O Port Address Map Each peripheral device in the system is assigned a set of I/O port addresses which also becomes the identity of the device. The following table lists the I/O port addresses used. Address Device Description 0x00000000-0x00000CF7 PCI bus 0x00000000-0x00000CF7...
  • Page 69 Appendix 0x000000BC-0x000000BD Programmable interrupt controller 0x000004D0-0x000004D1 Programmable interrupt controller 0x000004D0-0x000004D1 Motherboard resources 0x0000002E-0x0000002F Motherboard resources 0x0000004E-0x0000004F Motherboard resources 0x00000061-0x00000061 Motherboard resources 0x00000063-0x00000063 Motherboard resources 0x00000065-0x00000065 Motherboard resources 0x00000067-0x00000067 Motherboard resources 0x00000070-0x00000070 Motherboard resources 0x00000070-0x00000070 System CMOS/real time clock 0x00000080-0x00000080 Motherboard resources 0x00000080-0x00000080 Motherboard resources 0x00000092-0x00000092...
  • Page 70 Appendix 0x00000064-0x00000064 Standard 101/102-Key or Microsoft Natural PS/2 Keyboard 0x000003F8-0x000003FF Communications Port (COM1) 0x000002F8-0x000002FF Communications Port (COM2) 0x00000378-0x0000037F Printer Port (LPT1) 0x00000010-0x0000001F Motherboard resources 0x00000022-0x0000003F Motherboard resources 0x00000044-0x0000005F Motherboard resources 0x00000072-0x0000007F Motherboard resources 0x00000084-0x00000086 Motherboard resources 0x00000088-0x00000088 Motherboard resources 0x0000008C-0x0000008E Motherboard resources 0x00000090-0x0000009F Motherboard resources...

  • Page 71: Appendix B: Interrupt Request Lines (Irq)

    Appendix 0x000001CE-0x000001CF VgaSave 0x000002E8-0x000002EF VgaSave Appendix B: Interrupt Request Lines (IRQ) Peripheral devices use interrupt request lines to notify CPU for the service required. The following table shows the IRQ used by the devices on board. Level Function IRQ 9 Microsoft ACPI-Compliant System IRQ 16 PCI standard PCI-to-PCI bridge...

  • Page 72: Appendix C: Bios Memory Map

    Appendix Appendix C: BIOS Memory Map Address Device Description 0xA0000-0xBFFFF PCI bus 0xA0000-0xBFFFF VgaSave 0xD0000-0xD3FFF PCI bus 0xD4000-0xD7FFF PCI bus 0xD8000-0xDBFFF PCI bus 0xDC000-0xDFFFF PCI bus 0xE0000-0xE3FFF PCI bus 0xE4000-0xE7FFF PCI bus 0x7DA00000-0xFEAFFFFF PCI bus 0x7DA00000-0xFEAFFFFF Motherboard resources 0xF7800000-0xF7BFFFFF Video Controller (VGA Compatible) 0xE0000000-0xEFFFFFFF Video Controller (VGA Compatible) 0xF7C2B000-0xF7C2B00F...
  • Page 73 Appendix 0xFED19000-0xFED19FFF Motherboard resources 0xF8000000-0xFBFFFFFF Motherboard resources 0xFED20000-0xFED3FFFF Motherboard resources 0xFED90000-0xFED93FFF Motherboard resources 0xFED45000-0xFED8FFFF Motherboard resources 0xFEE00000-0xFEEFFFFF Motherboard resources 0x20000000-0x201FFFFF System board 0x40000000-0x401FFFFF System board - 69 -...

  • Page 74: Appendix D: Digital I/O Setting

    Appendix Appendix D: Digital I/O Setting Below are the source codes written in C, please take them for Digital I/O application examples. The default I/O address is 6Eh. C language Code SMBus Device Register Reader program by Rex Chin. */ /*----- Include Header Area -----*/ #include “math.h”...
  • Page 75 Appendix delay(3000); printf(“Digital I/O pin 6,4,2,0 LED OFF ...\n”); Index 11, GPIO1x Output Data value SMB_Byte_WRITE(SMB_PORT_AD,SMB_DEVICE_ADD,0x11,0x55); delay(1500); SMB_Byte_READ(int SMPORT, int DeviceID, int REG_INDEX) outportb(SMPORT+02, 0x00); /* clear */ outportb(SMPORT+00, 0xff); /* clear */ delay(10); outportb(SMPORT+04, DeviceID+1); /* clear */ outportb(SMPORT+03, REG_INDEX); /* clear */ outportb(SMPORT+02, 0x48);...

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