Kenwood DV-502 Service Manual page 8

DV-502/503/DVF-3050/3550
2-2 D/A Converter : PCM1748(IC801)
Pin No. Pin Name
1 BCK
2 DATA
3 LRCK
4 DGND
5 VDD
6 VCC
7 VOUTL
8 VOUTR
9 AGND
10 VCOM
11 ZEROR
12 ZEROL
13 MD
14 MC
15 ML
16 SCK
2-3 64 Bit SDRAM : KS641632D(IC301)
Pin No. Pin Name
38
37
19
20,21 BA0,BA1
23~26
A0~A11
29~35
18 WE,CAS,RAS
15,39 LDQM,UDQM
2,4,5,7,8,
10,11,13,42
DQ0~DQ15
44 45,47,48
50,51,53
9 VDD/VSS
10 VDDQ/VSSQ
11 NC
Block Diagram for D/A Converter
BCK Serial
LRCK Input
I/F
DATA
ML Function
MC Control
MDI I/F
System Clock
System
SCK
Clock
Manager
8
CIRCUIT DESCRIPTION
I/O
I Audio data bit clock input.
I Audio data digital input.
I Audio data latch enable input.
- Digital ground.
- Digital power supply (+3.3V).
- Analog power supply (+5V).
O Analog output for L-channel.
O Analog output for R-channel.
- Analog ground.
- Common voltage decoupling.
O Zero flag output for R-channel.
O Zero flag output for L-channel.
I Mode control data input.
I Mode control clock input.
I Mode control latch input.
I System clock input.
I/O
The system clock input. all other inputs are registered to the SDRAM on
CLK I
the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
CKE -
of the states among power down, suspend or self refresh.
CS - Enables or disables all inputs except CLK, CKE, and DQM.
Selects bank to be activated during RAS activity.
-
Selects bank to be read/written during CAS activity.
Row address : RA0~RA11, Column address : CA0~CA7
-
Auto-precharge flag : A10
- WE, CAS and RAS define the operation.
I/O Controls output buffers in read mode and masks input data in write mode.
I/O Multiplexed data input/output pin.
- Power supply for internal circuits and input buffers.
- Power supply for output buffers.
- Unused
8X
Oversampling Enhanced
Digital Filter Multi-level
with Delta-Sigma
Function Modulator
Controller
\Zero Detect
Description
Description
Output Amp and
DAC
Low-pass Filter
Output Amp and
DAC
Low-pass Filter
Power Supply
Vout L
Vcom
Vout R