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TDA4661 <1H DELAY LINE>
16
±(R-Y)
colour-difference
input signals
14
±(B-Y)
9
Vp1
analogue supply
5
sandcstle
pulse input
TA8859AP <DEFLECTION CORRECTION>
LA7833 <VERTICAL OUTPUT>
V-DRIVE PLS
INPUT
SIGNAL
CLAMPING
LINE
MEMORY
pre-amplifiers
SIGNAL
CLAMPING
LINE
MEMORY
FREQUENCY
SANDCASTLE
PHASE
DETECTOR
DETECTOR
10
GND1
14
16
15
PULSE
RAMP
SHAPER
AGC
∫
CORRECT
PALABOLA
CORR.
1
2
3
VCC
6
4
VERTICAL
DRIVE
1
5
GND
SAMPLE-
AND-
HOLD
SAMPLE-
AND-
HOLD
3MHz shifting clock
TDA4661
DIVIDER
BY 192
6 MHz
LP
CCO
digital supply
1
Vp2
13
11
12
PULSE INFERFACE
TRIGGER
LINEARUTY
S-C CORR.
CORRECTION
ETH
ETH
CORR.
CORR.
4
5
6
3
PUMP UP
VERTICAL
OUTPUT
THERMAL
PROTECTION
LA7833
-8-
11
LP
addition
colour-difference
stages
output
output sugnals
buffers
12
LP
2
n.c.
6
n.c.
13
n.c.
n.c.
15
DIVIDER
7
i.c.
BY 2
3
4,8
GND2
9
10
TA8859AP
7
8
7
2
V-OUTPUT
±(R-Y)
±(B-Y)
F2KT/KV
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