Atmel SpaceWire Router SpW-10X User Manual
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Atmel SpaceWire Router SpW-10X User Manual

Atmel corp. spacewire router user manual
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SpaceWire Router

User Manual

SpW-10X SpaceWire Router
User Manual
UoD_SpW-10X_UserManual
AT7910E
Issue 3.4
th
11
July 2008
Chris McClements, University of Dundee
Steve Parkes, University of Dundee
Gerald Kempf, Austrian Aerospace
Steve Parkes, University of Dundee
Pierre Fabry, ESTEC
Preliminary
SpW-10X
Ref.:
UoD_SpW-10X_
UserManual
Issue: 3.4
th
Date:
11
July 2008
1

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Summary of Contents for Atmel SpaceWire Router SpW-10X

  • Page 1: User Manual

    SpW-10X SpaceWire Router Ref: Atmel Part No.: Document Revision: Date: Prepared by - Chris McClements, University of Dundee Steve Parkes, University of Dundee Gerald Kempf, Austrian Aerospace Checked by - Steve Parkes, University of Dundee ESA Manager - Pierre Fabry, ESTEC...

  • Page 2: Document Change Log

    Added sections on ASIC pin placement, ASIC power consumption, bias resistors, phase locked loop and anomalies. Modifications before handed to Atmel Modifications to SpaceWire signal names (Map pin 1 to 0) Updates as user manual. Changed document name to UoD_SpW_10X_UserManual.doc...
  • Page 3 January 2008 Issue 3.1 April 2008 Issue 3.2 April 2008 Issue 3.3 July Issue 3.4 SpW-10X SpaceWire Router User Manual guidelines. Section added on anomalies and warnings. Section added on Technical Support. Corrections and example schematic improved. Explanation of non-blocking cross bar switch added.

  • Page 4: Table Of Contents

    CONTENTS CONTENTS...4 LIST OF FIGURES ... 10 LIST OF TABLES ... 12 INTRODUCTION... 14 TERMS, ACRONYMS AND ABBREVIATIONS ... 14 DOCUMENTS ... 15 USER APPLICATIONS ... 16 STAND-ALONE ROUTER ... 16 NODE INTERFACE ... 17 EMBEDDED ROUTER... 17 EXPANDING THE NUMBER OF ROUTER PORTS ... 18 FUNCTIONAL OVERVIEW ...
  • Page 5 EXTERNAL PORT DATA SIGNALS... 37 TIME-CODE SIGNALS ... 39 STATUS INTERFACE SIGNALS... 41 RESET CONFIGURATION SIGNALS ... 42 POWER, GROUND, PLL AND LVDS SIGNALS ... 45 5.7.1 General... 45 5.7.2 Decoupling ... 45 5.7.3 LVDS Reference ... 45 5.7.4 PLL External Components ... 45 INTERFACE OPERATIONS...
  • Page 6 8.1.2 Auto-Start ... 79 8.1.3 Link-Start... 79 8.1.4 Link-Disable ... 80 8.1.5 Automatic deactivate driver mode... 80 8.1.6 Setting the SpaceWire port transmit data rate ... 82 GLOBAL SPACEWIRE LINK CONTROL ... 84 8.2.1 Start on request mode... 85 8.2.2 Disable on Silence mode ...
  • Page 7 9.5.5 Time-Code Register ... 121 9.5.6 Device Manufacturer and Chip ID Register ... 122 9.5.7 General Purpose Register... 123 9.5.8 Time-Code Enable Register... 123 9.5.9 Transmit Clock Control Register ... 124 9.5.10 Destination Key Register... 127 9.5.11 Unused Registers and Register Bits ... 127 9.5.12 Empty packets...
  • Page 8 12.2.7 External Ports... 141 12.2.8 Time-code Interface ... 141 12.2.9 Status / Power On Configuration Interface ... 141 12.2.10 PLL ... 142 ANOMALIES AND WARNINGS... 143 13.1 ANOMALIES ... 143 13.2 WARNINGS ... 143 13.3 RESET ANOMALY... 145 13.3.1 Data Strobe Reset Waveform ... 145 13.3.2 Data Strobe Disable Waveform ...

  • Page 9: Spacewire Router

    15.16 ISSUE 1.2 TO ISSUE 1.3... 154 15.17 ISSUE 1.1 TO ISSUE 1.2... 155 15.18 ISSUE 1.0 TO ISSUE 1.1... 155 SpW-10X SpaceWire Router User Manual Preliminary Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: July 2008...

  • Page 10: List Of Figures

    LIST OF FIGURES 2-1 S IGURE TAND LONE OUTER 2-2 N ... 17 IGURE NTERFACE 2-3 E ... 18 IGURE MBEDDED OUTER 2-4 E IGURE XPANDING THE NUMBER OF 2-5 E IGURE XPANDING THE NUMBER OF 3-1 S IGURE PACE IRE ROUTER BLOCK DIAGRAM 5-1 LVDS R IGURE...

  • Page 11: User Manual Date

    8-8 A IGURE RBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY 8-9 A IGURE RBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY 8-10 N IGURE ORMAL GROUP ADAPTIVE ROUTING 8-11 G IGURE ROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY 8-12 G IGURE ROUP ADAPTIVE ROUTING WHEN PORTS NOT READY 8-13 P IGURE...

  • Page 12: List Of Tables

    13-5 L IGURE ISCONNECT 13-6 D IGURE ATA AFTER PARITY ERROR ANOMALY 13-7 N IGURE O ERROR END OF PACKET INSERTED AFTER PARITY ERROR LIST OF TABLES 1-1 A ABLE PPLICABLE OCUMENTS 1-2 R ABLE EFERENCE OCUMENTS 5-1 G ... 32 ABLE LOBAL IGNALS...
  • Page 13 9-6 S ABLE PACE ONTROL 9-7 E ABLE XTERNAL ONTROL 9-8 N ABLE ETWORK ISCOVERY 9-9 R ABLE OUTER DENTITY EGISTER 9-10 R ABLE OUTER ONTROL EGISTER 9-11 E ABLE RROR CTIVE EGISTER 9-12 T ABLE EGISTER 9-13 D ABLE EVICE ANUFACTURER AND 9-14 T...

  • Page 14: Introduction

    1. INTRODUCTION This document is a technical reference for the implementation and operation of the SpW-10X SpaceWire Router device (Atmel part number AT7910E). Note: Detailed timing information for the ASIC implementation will be available in 1Q08. 1.1 TERMS, ACRONYMS AND ABBREVIATIONS 3.3 volt interface levels.

  • Page 15: Documents

    Application Note AN-1194, Failsafe Biasing of LVDS Interfaces, Downloadable from: http://www.national.com/an/AN/AN- 1194.pdf#page=1 MH1RT Rad Hard 1.6M Used Gates 0.35 Micron CMOS Sea of Gates / Embedded Gates ASIC families. Downloadable from: http://www.atmel.com/dyn/resources/prod_documen ts/doc4110.pdf Preliminary Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: July 2008...

  • Page 16: User Applications

    2. USER APPLICATIONS The SpW-10X SpaceWire router device may be used in several different ways as described in the following sub-sections. Note: SpW-10X is pronounced “SpaceWire Ten X”. This name derives from the abbreviation for SpaceWire (SpW), the fact that the router has eight SpaceWire ports and two external ports giving ten ports in total, and the used of “X”...

  • Page 17: Node Interface

    2.2 NODE INTERFACE The SpaceWire Router has two external ports which enable the device to be used as a node interface. The equipment to be connected to the SpaceWire network is attached to one or both external ports. One or more SpaceWire ports are used to provide the connection into the SpaceWire network. Unused SpaceWire ports may be disabled and their outputs deactivated to save power.

  • Page 18: Expanding The Number Of Router Ports

    Instrument Instrument Instrument Instrument Instrument Instrument In Figure 2-3 a SpaceWire system similar to that shown in Figure 2-1 is shown with the SpW-10X router embedded in a SpaceWire node along with a processor. The processor interfaces can interface to the SpW-10X router using the external FIFO ports saving some SpaceWire ports for connecting to additional instruments.
  • Page 19 SpaceWire Ports Figure 2-4 Expanding the number of SpaceWire Ports (1) Figure 2-4 shows a pair of SpW-10X routers connected together using the external FIFO ports to provide a 16 port router. A small amount of external logic is required to connect the external FIFO ports in this way.
  • Page 20 Figure 2-5 Expanding the number of SpaceWire Ports (2) Figure 2-5 shows two SpW-10X router devices interconnected using two of the SpaceWire ports on each router. This leaves twelve SpaceWire ports for connection to other SpaceWire nodes. The External FIFO ports of each router are used to connect to user logic in an FPGA or to a processing device.

  • Page 21: Functional Overview

    3. FUNCTIONAL OVERVIEW A SpaceWire routing switch comprises a number of SpaceWire ports and a routing matrix. The routing matrix enables packets arriving at one SpaceWire port to be transferred to and sent out of another port on the routing switch. A SpaceWire routing switch is thus able to connect together many SpaceWire nodes, providing a means of routing packets between the nodes connected to it.

  • Page 22: Spacewire Ports

    SpaceWi re Po rt 1 SpaceWi re Po rt 2 SpaceWi re Po rt 3 SpaceWi re Po rt 4 Spa ce Wire SpaceWi re Po rt 5 Inter fac es SpaceWi re Po rt 6 SpaceWi re Po rt 7 SpaceWi re Po rt 8 Exte rna l...

  • Page 23: Configuration Port

    written to or read from synchronously with the 30MHz system clock. An eight-bit data interface and an extra control bit for end of packet markers are provided by each external port FIFO. Packets received by the external port are routed by the routing control logic to the configuration port, SpaceWire link ports or the other external port dependent on the packet address.

  • Page 24: Time-Code Processing

    The crossbar switch connects an input port to an output port allowing data to flow from the input port to the output port. Several input ports may be connected simultaneously to several output ports all passing data. Two or more input ports may not be connected to a single output port. The crossbar switch is a “non-blocking”...

  • Page 25: Pin Locations

    4. PIN LOCATIONS The SpaceWire router package is a 196 pin MQFPF package. Type definition: - 3V3...3.3 Volt power - GND...Ground - PIC... CMOS input - PRD4 ... pull-down resistor (min.16kΩ, max. 80kΩ) - PLL ... PLL pins - PFILVDSZP... LVDS cold sparing input - PFILVDSZPB ...
  • Page 26 DINMinus(1) SINPlus(1) SINMinus(1) SOUTMinus(1) SOUTPlus(1) DOUTMinus(1) DOUTPlus(1) DINPlus(2) DINMinus(2) SINPlus(2) SINMinus(2) VSSB VDDB SOUTMinus(2) SOUTPlus(2) DOUTMinus(2) DOUTPlus(2) DINPlus(3) DINMinus(3) SINPlus(3) SINMinus(3) SOUTMinus(3) SOUTPlus(3) VSSB VSSA2 VDDA2 VDDB DOUTMinus(3) DOUTPlus(3) DINPlus(4) DINMinus(4) LVDSRef SINPlus(4) SINMinus(4) SOUTMinus(4) SOUTPlus(4) DOUTMinus(4) DOUTPlus(4) VSSA3 VDDA3 SpW-10X SpaceWire Router User Manual...
  • Page 27 VSSB VDDB DINPlus(5) DINMinus(5) SINPlus(5) SINMinus(5) SOUTMinus(5) SOUTPlus(5) DOUTMinus(5) DOUTPlus(5) DINPlus(6) DINMinus(6) SINPlus(6) SINMinus(6) VSSB VDDB SOUTMinus(6) SOUTPlus(6) DOUTMinus(6) DOUTPlus(6) DINPlus(7) DINMinus(7) SINPlus(7) SINMinus(7) SOUTMinus(7) SOUTPlus(7) VSSB VDDB DOUTMinus(7) DOUTPlus(7) DINPlus(8) DINMinus(8) SINPlus(8) VSSA4 VDDA4 SINMinus(8) SOUTMinus(8) SOUTPlus(8) DOUTMinus(8) DOUTPlus(8) SpW-10X SpaceWire Router User Manual...
  • Page 28 VSSB VDDB EXTOUTDATA9(0) EXTOUTDATA9(1) EXTOUTDATA9(2) EXTOUTDATA9(3) EXTOUTDATA9(4) VSSA5 VDDA5 EXTOUTDATA9(5) VSSB VDDB EXTOUTDATA9(6) EXTOUTDATA9(7) EXTOUTDATA9(8) EXTOUTEMPTYN9 EXTOUTREADN9 EXTINDATA9(0) EXTINDATA9(1) EXTINDATA9(2) EXTINDATA9(3) EXTINDATA9(4) EXTINDATA9(5) EXTINDATA9(6) EXTINDATA9(7) EXTINDATA9(8) EXTINFULLN9 VSSB VDDB EXTINWRITEN9 EXTOUTDATA10(0) EXTOUTDATA10(1) EXTOUTDATA10(2) EXTOUTDATA10(3) EXTOUTDATA10(4) EXTOUTDATA10(5) VSSB VDDB EXTOUTDATA10(6) EXTOUTDATA10(7) SpW-10X SpaceWire Router User Manual...
  • Page 29 EXTOUTDATA10(8) EXTOUTEMPTYN10 VSSA6 VDDA6 EXTOUTREADN10 EXTINDATA10(0) EXTINDATA10(1) EXTINDATA10(2) EXTINDATA10(3) EXTINDATA10(4) EXTINDATA10(5) EXTINDATA10(6) EXTINDATA10(7) EXTINDATA10(8) EXTINFULLN10 EXTINWRITEN10 VSSA7 VDDA7 VSSB VDDB EXTTICKIN EXTTIMEIN(0) EXTTIMEIN(1) EXTTIMEIN(2) EXTTIMEIN(3) EXTTIMEIN(4) EXTTIMEIN(5) EXTTIMEIN(6) EXTTIMEIN(7) SELEXTTIME TIMECTRRST EXTTICKOUT EXTTIMEOUT(0) EXTTIMEOUT(1) EXTTIMEOUT(2) EXTTIMEOUT(3) VSSB VDDB EXTTIMEOUT(4) EXTTIMEOUT(5) SpW-10X SpaceWire Router User Manual...
  • Page 30 EXTTIMEOUT(6) EXTTIMEOUT(7) STATMUXADDR(0) STATMUXADDR(1) STATMUXADDR(2) STATMUXADDR(3) VSSB VDDB STATMUXOUT(0) STATMUXOUT(1) STATMUXOUT(2) VSSA8 VDDA8 STATMUXOUT(3) STATMUXOUT(4) STATMUXOUT(5) STATMUXOUT(6) STATMUXOUT(7) VSSB SpW-10X SpaceWire Router User Manual PO44F Time-code output PO44F Time-code output Status output multiplexer address Status output multiplexer address Status output multiplexer address Status output multiplexer address Ground Power...

  • Page 31: Device Interface

    5. DEVICE INTERFACE The device pins used by each interface are described in this section. There is a table for each type of interface listing the signals in that interface. These tables have the following fields: Pin No: The device pin number Signal: The name of the signal Dir:...

  • Page 32: Spacewire Signals

    PinNo Signal RST_N TestIOEn TestEn FEEDBDIV(2) FEEDBDIV(1) FEEDBDIV(0) See section 10.1 for timing details. Simultaneous data/strobe transitions can occur during reset and power up. This is not a problem when connected to SpaceWire compliant devices but is a problem when connected to IEEE-1355 devices. 5.2 SPACEWIRE SIGNALS 5.2.1 SpW-10X SpaceWire Signals The SpaceWire interface signals are listed in Table 5-2.
  • Page 33 Table 5-2 Data and Strobe SpaceWire Signals PinNo Signal DOUTPlus(1) DOUTMinus(1) DOUTPlus(2) DOUTMinus(2) DOUTPlus(3) DOUTMinus(3) DOUTPlus(4) DOUTMinus(4) DOUTPlus(5) DOUTMinus(5) DOUTPlus(6) DOUTMinus(6) DOUTPlus(7) DOUTMinus(7) DOUTPlus(8) DOUTMinus(8) SOUTPlus(1) SOUTMinus(1) SOUTPlus(2) SOUTMinus(2) SOUTPlus(3) SOUTMinus(3) SOUTPlus(4) SOUTMinus(4) SOUTPlus(5) SOUTMinus(5) SOUTPlus(6) SOUTMinus(6) SOUTPlus(7) SOUTMinus(7) SOUTPlus(8) SOUTMinus(8) SpW-10X SpaceWire Router...
  • Page 34 DINPlus(1) DINMinus(1) DINPlus(2) DINMinus(2) DINPlus(3) DINMinus(3) DINPlus(4) DINMinus(4) DINPlus(5) DINMinus(5) DINPlus(6) DINMinus(6) DINPlus(7) DINMinus(7) DINPlus(8) DINMinus(8) SINPlus(1) SINMinus(1) SINPlus(2) SINMinus(2) SINPlus(3) SINMinus(3) SINPlus(4) SINMinus(4) SINPlus(5) SINMinus(5) SINPlus(6) SINMinus(6) SINPlus(7) SINMinus(7) SINPlus(8) SINMinus(8) See section 10.2 for timing details. SpW-10X SpaceWire Router User Manual Differential input pair, data part of Data-Strobe SpaceWire port 1.

  • Page 35: Spacewire Input Fail Safe Resistors

    5.2.2 SpaceWire Input Fail Safe Resistors If a SpaceWire input becomes disconnected then no current flows through the termination resistor. The differential voltage across this resistor is then zero. A small noise current, induced by electro- magnetic interference on PCB tracks or on any part of the SpaceWire cable still attached to the receiver, will cause a small differential voltage across the termination resistor.
  • Page 36 The bias resistor values are determined as follows: 1. Determine the amount of noise protection required. E.g. if the maximum noise voltage expected is less than 10 mV then the bias current required is I mV/100 Ω = 0.1 mA. Note: the bias current should be at least an order of magnitude lower than the 3 mA current loop used for normal LVDS operation.

  • Page 37: Operation With 5V Powered Lvds Devices

    5.2.3 Operation with 5V Powered LVDS Devices Since LVDS is based on a current loop it should not matter what the supply voltage is to an LVDS device connected to the SpW-10X router. However, there is a potential problem when connecting to devices with power supplies greater than 3.3 V, which is the supply voltage of the SpW-10X device.
  • Page 38 EXT9_IN_DATA(5) EXT9_IN_DATA(4) EXT9_IN_DATA(3) EXT9_IN_DATA(2) EXT9_IN_DATA(1) EXT9_IN_DATA(0) EXT9_IN_FULL_N EXT9_IN_WRITE_N EXT10_OUT_DATA(8) EXT10_OUT_DATA(7) EXT10_OUT_DATA(6) EXT10_OUT_DATA(5) EXT10_OUT_DATA(4) EXT10_OUT_DATA(3) EXT10_OUT_DATA(2) EXT10_OUT_DATA(1) EXT10_OUT_DATA(0) EXT10_OUT_EMPTY_N EXT10_OUT_READ_N EXT10_IN_DATA(8) EXT10_IN_DATA(7) EXT1-_IN_DATA(6) EXT10_IN_DATA(5) EXT10_IN_DATA(4) SpW-10X SpaceWire Router User Manual (8)(7...0) – Bits (0)(dddddddd) - Data byte (1)(XXXXXXX0) - EOP. (1)(XXXXXXX1) - EEP. Bit 7 is the most significant bit of the data byte.

  • Page 39: Time-Code Signals

    EXT10_IN_DATA(3) EXT10_IN_DATA(2) EXT10_IN_DATA(1) EXT10_IN_DATA(0) EXT10_IN_FULL_N EXT10_IN_WRITE_N See section 6.1 for information on the operation of the external ports and section 10.3 for timing details. 5.4 TIME-CODE SIGNALS The time-code interface signals are listed in Table 5-4. The timing of this interface is shown in Figure 6-3 and Figure 6-4.
  • Page 40 EXT_TIME_IN(7) EXT_TIME_IN(6) EXT_TIME_IN(5) EXT_TIME_IN(4) EXT_TIME_IN(3) EXT_TIME_IN(2) EXT_TIME_IN(1) EXT_TIME_IN(0) SEL_EXT_TIME TIME_CTR_RST EXT_TICK_OUT EXT_TIME_OUT(7) EXT_TIME_OUT(6) EXT_TIME_OUT(5) EXT_TIME_OUT(4) EXT_TIME_OUT(3) SpW-10X SpaceWire Router User Manual should be pulled down (e.g. 4k7 Ω). EXT_TIME_IN(7:0) provides the value of the time- code to be distributed by the router when an external time-code source is selected i.e.

  • Page 41: Status Interface Signals

    EXT_TIME_OUT(2) EXT_TIME_OUT(1) EXT_TIME_OUT(0) See section 6.2 for information on the operation of the time-code interface and section 10.4 for timing details. 5.5 STATUS INTERFACE SIGNALS The status interface signals are listed in Table 5-5. Table 5-5 Link error indication Signals PinNo Signal STAT_MUX_ADDR(3)

  • Page 42: Reset Configuration Signals

    STAT_MUX_OUT Figure 5-2 Configuration interface timing specification The POR configuration signals (POR_SIGNALS) listed in Table 5-6 are loaded into the appropriate internal configuration registers of the router after RST is de-asserted. To make sure that the POR configuration signal values are loaded properly they should be held stable for at least three CLK cycles following RST being de-asserted.
  • Page 43 Table 5-6 Reset Configuration Signals Signal STAT_MUX_OUT(2:0) [maps to -> POR_TX_RATE(2:0)] STAT_MUX_OUT(3) [maps to -> POR_ADDR_SELF_N STAT_MUX_OUT(4) [maps to -> POR_TIMEOUT_EN_N] STAT_MUX_OUT(5) [maps to -> POR_SEL_TIMEOUT0_N] SpW-10X SpaceWire Router User Manual Description Sets the transmitter maximum data rate after reset. The data rate can subsequently be changed during normal operation using port configuration commands.
  • Page 44 STAT_MUX_OUT(6) [maps to -> POR_START_ON_REQ_N] STAT_MUX_OUT(7) [maps to -> POR_DSBLE_ON_SILENCE_N] In most onboard applications it is recommended to have Stat_mux_out(4) pulled low by default in order to enable the watchdog timers on reset. When the watchdog timers are not enabled the SpaceWire and external ports can block indefinitely if, for example, a source stops sending data in the middle of a packet.

  • Page 45: Power, Ground, Pll And Lvds Signals

    Note: The recommended method for setting the POR signals is to use external pull up/down resistors (e.g. 4k7 Ω) in which case the timing of the POR signals is not critical. See section 6.3 and 6.4 for further information on the operation of the status/ power on configuration interface and section 10.5 for timing details.
  • Page 46 Figure 5-3 PLL with external components The PLL loop filter component values to be used are R = 10 kΩ C = 120 pF C0 = 3.3 pf. The VCO bias resistor depends on the required VCO frequency range which is determined by the PLL feedback divider (NF in Figure 5-3).

  • Page 47: Interface Operations

    6. INTERFACE OPERATIONS This section describes the operation of the external FIFO port, time-code interface and status/power on configuration interface. First a note on the terminology used: Signals are given a name (e.g. EXT_IN_FULL) and a logic level (e.g. _N). The term asserted is used when the signal state reflects the signal name e.g. EXT_IN_FULL is asserted when the external input FIFO is full.

  • Page 48: Time-Code Interface Operation

    EXT_OUT_READ_Nx EXT_OUT_DATAx EXT_OUT_EMPTY_Nx Figure 6-2 External port read timing specification Reading of the External port is illustrated in Figure 6-2. When data is available in the External port FIFO then it is placed on the EXT_OUT_DATA bus and the EXT_OUT_EMPTY_N signal is asserted to signal to the external system that data is available.

  • Page 49: Status Interface Operation

    SEL_EXT_TIME signal when EXT_TICK_IN signal has a rising edge. If SEL_EXT_TIME is 1 then the EXT_TIME_IN(7:0) inputs are used to provide the contents of the time-code. If SEL_EXT_TIME is 0 then the internal time-code counter provides the least-significant 6-bits of the time-code and the EXT_TIME_IN(7:6) inputs provide the most-significant 2-bits.
  • Page 50 Table 6-1 Multiplexed Status Pins Bit Assignment Status Register Address Configuration Port 1 - 8 SpaceWire Ports 1 - 8 respectively 9 - 10 External Ports 0 - 1 respectively Network Discovery Router Identity Router Control SpW-10X SpaceWire Router User Manual Status Signal Packet return address error Output port timeout error...

  • Page 51: Reset Configuration Interface Operation

    Error Active Time-code General Purpose 6.4 RESET CONFIGURATION INTERFACE OPERATION CL K RSTN POR_ SIGNA L S Figure 6-7 Reset configuration interface timing specification The POR configuration signals (POR_SIGNALS) listed above are loaded into the appropriate internal configuration registers of the router on the first rising edge of the system clock, CLK, after RSTN is de- asserted.

  • Page 52: Spacewire Router Packet Types

    7. SPACEWIRE ROUTER PACKET TYPES This section describes how the routing control logic interprets packets. 7.1 PACKET ADDRESSES The routing control logic interprets the first byte of each received packet as the packet address. The packet address defines the physical ports through which the routing control logic will use to route the packet towards its destination.

  • Page 53: Packet Priority

    7.2 PACKET PRIORITY Each packet which is input to the router has an associated priority level, either as a result of the packet address or the internal routing table. Two priority levels HIGH and LOW are supported. The table below defines the priority levels for packet addresses Packet Address 11-31 32-255...

  • Page 54: Invalid Addresses

    Table 7-3 Packet Header Deletion Mapping Packet Address Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled 11-31 32-255 Dependent on routing table (default not enabled) Note that header deletion is always enabled for path addresses and cannot be changed by configuration.

  • Page 55: Data Packets

    7.5 DATA PACKETS Packets which have addresses in the range 1 to 255 are routed to the SpaceWire ports and the external ports dependent on the packet address. Data packets have an address header byte a cargo field and an end of packet marker. The normal packet structure is show below. ADDRESS 1-255 Figure 7-1 Normal router data packets...

  • Page 56: Read Command

    Table 7-4 Supported RMAP Command Codes RMAP Command Code “0000” Not used “0001” Not used “0010” Read single address “0011” Read incrementing address “0100” Not used “0101” Not used “0110” Not used “0111” Read-modify-write incrementing address “1000” Write single address, no verify, no acknowledge “1001”...
  • Page 57 Table 7-5 Read Single Address Characteristics Action 8-bit read 16-bit read 32-bit read 64-bit read Word or byte address Accepted Logical Addresses Accepted destination keys Accepted address ranges Address Incrementation The RMAP read single address command is supported in the SpaceWire router. The single address command is used to read a single 32 bit register location from the router registers.
  • Page 58 Table 7-6 Read Single Address Command Packet Fields Field Config Port The configuration port address field routes the packet to the configuration Address port of the router. The configuration port address (00h) is always present when configuring the SpaceWire Router. Destination The destination logical address field is not used in the SpaceWire Router.
  • Page 59 Length one 32 bit register location. Header The header CRC is the eight bit CRC code used to detect errors in the command packet. The CRC code is checked before the command is executed In Figure 7-4 the format of the reply to a read single address command is illustrated. The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address.

  • Page 60: Read Incrementing Command

    Protocol The RMAP protocol identifier value 01h. Identifier Command Read single address reply command byte. The packet type bits in the Byte command byte indicate this packet is a response packet. Status The command status is returned in this field. The command status can be command successful or an RMAP error code as defined in section 7.6.6.
  • Page 61 Table 7-8 Read Incrementing Address Characteristics Action 8-bit read 16-bit read 32-bit read 64-bit read Word or byte address Accepted Logical Addresses Accepted destination keys Accepted address ranges Incrementing address The RMAP read incrementing address command is supported in the SpaceWire router. The read incrementing address is used to read a continuous block of registers from the SpaceWire router, e.g.
  • Page 62 In Figure 7-5 the first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address. Fields which are depicted in bold text are expected values. Fields which are shaded are optional. Destination Logical Address Source Path Address Source Logical Address Read Address (MS)
  • Page 63 Destination The destination key identifier must match the contents of the destination key register, see section 9.5.10. Source The source path address field is used to add source path addresses to the Path head of the reply packet. The expected number of source path addresses is Address specified in the command byte.
  • Page 64 In Figure 7-6 the format of the reply to a read incrementing address command is illustrated. The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address. Fields which are depicted in bold text are expected values. Fields which are shaded are optional.

  • Page 65: Read Modify Write Command

    Command Read incrementing address reply command byte. The packet type bits in the Byte command byte indicate this packet is a reply packet. Status The command status is returned in this field. The command status can be command successful or an RMAP error code as defined in section 7.6.6. Destination The destination logical address is set to the default value FEh as the logical...
  • Page 66 32-bit read-modify-write 64-bit read-modify-write Word or byte address Accepted Logical Addresses Accepted destination keys Accepted address ranges Incrementing address The RMAP read-modify-write command is supported by the SpaceWire router. The read modify write command is used to set or reset a single or number of bits in a router register. The Read-Modify-Write command is useful when it is desirable to set a link register setting without upsetting the other settings in one command, i.e.
  • Page 67 Table 7-12 Read-Modify-Write Command Packet Fields Packet Field Config Port The configuration port address field routes the packet to the configuration Address port of the router. The configuration port address is always present when configuring the SpaceWire Router. Destination The destination logical address is not used in the SpaceWire Router. The Logical SpaceWire router accepts packets which have the default destination logical Address...
  • Page 68 Mask 4 bytes for the mask to modify a 32-bit register. Length Header The header CRC used to detect errors in the header part of the command packet. Data and The data and mask values to write to the SpaceWire router. The data is Mask written dependent on the mask as shown in Figure 7-8.
  • Page 69 In Figure 7-9 the format of the reply to a Read-Modify-Write command is illustrated. The first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address. Fields which are depicted in bold text are expected values. Fields which are shaded are optional.

  • Page 70: Write Command

    logical address SpaceWire router does not have a logical address. Transaction The transaction identifier identifies the command packet and reply packet Identifier with a unique number. The transaction identifier in the reply packet is copied from the command packet and returned in this field, so that the command and the corresponding reply have the same transaction identifier value.
  • Page 71 The RMAP write single address, with data verify and acknowledgement command is supported in the SpaceWire router. The RMAP write command is used to write a 32 bit value into one of the SpaceWire router registers. In Figure 7-10 the first byte received by the SpaceWire router configuration logic is the port address followed by the destination logical address.
  • Page 72 Command The command byte indicates a write single address, with verification and Byte acknowledgement packet. The Source path address length fields are set to the number of source path addresses required as defined in section 7.6.9. Destination The destination key identifier must match the contents of the destination key register, see section 9.5.10.
  • Page 73 In Figure 7-11 the format of the reply to a write command is illustrated. The first byte sent by the SpaceWire router configuration logic is the port address followed by the destination logical address. Fields which are depicted in bold text are expected values. Fields which are shaded are optional. Note that the reply is always sent out of the same port as the command was received on.

  • Page 74: Command Error Response

    address Transaction The transaction identifier identifies the command packet and reply packet with a Identifier unique number. The transaction identifier in the reply packet is copied from the command packet and returned in this field, so that the command and the corresponding reply have the same transaction identifier value.
  • Page 75 packet is corrupted Early EOP The command packet was terminated early with an EOP. A reply packet is sent if the early EOP error occurs on the data part of the packet Cargo too Large The expected amount of SpaceWire cargo has been received without receiving an EOP marker Early EEP...

  • Page 76: Command Packet Cyclic Redundancy Check

    incrementing read 4. The data length is not 4 in a verified write command. 5. The data length is not 8 in a read modify write command. Invalid Register The address field is Address addressing an unknown register for a read command or a read only register in a write command.

  • Page 77: Source Path Address Field

    7.6.9 Source Path Address Field The RMAP command field “source path address length” indicates the number of source path addresses which are expected in the packet. Up to 12 source path addresses can be accepted by the router configuration port. The source path addresses shall be decoded by the SpaceWire router as follows.

  • Page 78: Command Packet Fill Bytes

    Figure 7-12 and Figure 7-13 illustrate how source path addresses are returned in relation to the RMAP packet description. Dest Logical Source Logical Figure 7-12 Source Path Address field decoding Source Logical Figure 7-13 Source Path Addresses in Reply Packet 7.6.10 Command Packet Fill Bytes The Configuration port accepts packets which are addressed to port 0.

  • Page 79: Control Logic And Operational Modes

    8. CONTROL LOGIC AND OPERATIONAL MODES In this section the SpaceWire router control logic and operational modes are defined. The router control logic determines how the SpaceWire link ports operate, how received packets are routed to their destination and how the timeout mechanism detects packet blockages in the router. 8.1 SPACEWIRE LINK CONTROL Each of the eight SpaceWire links has an associated SpaceWire control register.

  • Page 80: Link-Disable

    8.1.4 Link-Disable The SpaceWire port can be disabled therefore rendering the link unusable. When a SpaceWire link which is running is disabled it will disconnect from the far end and refuse connection attempts by the far end of the link. Caution should be used when using this command for a stand alone router as disabling all the links will leave the router unusable, except through a reset operation.
  • Page 81 Deactivated DOUT Deactivated SOUT Figure 8-1 Deactivate driver operating mode Note the DOUT deactivate driver/disable is performed one CLK cycle before the SOUT deactivate, avoiding any simultaneous transitions on Data or Strobe. When the LVDS drivers are deactivated the equivalent circuit of these outputs is a shown in Figure 8-2.

  • Page 82: Setting The Spacewire Port Transmit Data Rate

    2850 Ω 91 µA Figure 8-3 Deactivated LDVS driver output connected to external bias network on LVDS input Current can now flow from the 3.3 volt supply to ground. When the bias resistors for 10mV noise margin are used, the total current flowing out of the LVDS outputs is around 200 µA as illustrated in Figure 8-3 The deactivate mode (see also section 9.4.3) does not tri-state the LVDS outputs.
  • Page 83 ⎛ ⎛ ⎜ ⎜ ⎝ ⎜ MbitRate ⎜ ⎜ ⎝ To provide a SpaceWire signal with a nominal 50/50 duty cycle, TXRATE and TX10MbitDIV should be even integers. Not all values of FEEDBDIV, TXDIV and TXRATE give valid clock signals. Table 8-1shows the recommended values to use to achieve a range of SpaceWire transmit data rates.

  • Page 84: Global Spacewire Link Control

    The columns header TXRATE give the SpaceWire transmit data rate obtained for various settings of the TXRATE field in a SpaceWire port control register. The duty cycle of the SpaceWire data rate clock is given in the row immediately underneath the TXRATE values. If the duty cycle is not 1:1 then one bit period will be shorter than the next, as for the 10 Mbits/s data rate.

  • Page 85: Start On Request Mode

    8.2.1 Start on request mode The Start on Request mode is enabled by setting the CFG_START_ON_REQ bit in the router control register. The input signal POR_START_ON_REQ_N determines the power on or reset state of the CFG_START_ON_REQ bit. When a SpaceWire packet is received which is to be routed out of a SpaceWire port that is not running it would normally be discarded.

  • Page 86: Control Logic And Routing

    Packet with address 2 The SpaceWire router Disable on Silence mode is used to disable a SpaceWire link when it no longer has any data to transfer. The Disable on Silence mode is enabled only when the router timeouts are enabled.

  • Page 87: Arbitration Of Packets With Matching Priority (1)

    dependent on the previous input port which had access to that output port. The next input port to transfer data to an output port is the next highest port number (modulo number of ports) that has data to send. Thus the input port which previously had access to the output port will be selected last by the router control logic.

  • Page 88: Arbitration Of Packets With Matching Priority (2)

    8.3.2.2 Arbitration of packets with matching priority (2) In the Figure 8-7 another example of arbitrating between packets with the same priority is illustrated. Again only router ports 1-5 are shown for clarity. At stage one input ports 1 and 3 have packets to be routed to output port 5. The previous input port to use output port 5 was input port 3 therefore the next input port to be selected by output port 5 will be input port 1 (assuming input ports 6, 7, 8, 9, 10 and 0 are not requesting to use the port).

  • Page 89: Arbitration Of Packets With Different Priority (1)

    8.3.2.3 Arbitration of packets with different priority (1) In the Figure 8-8 arbitration of packets with different priority is illustrated. Only router ports 1-5 are shown for clarity. At stage one input ports 1 and 3 have packets with logical addresses 80 and 52 respectively, which are both to be routed to output port 5.

  • Page 90: Arbitration Of Packets With Different Priority (2)

    8.3.2.4 Arbitration of packets with different priority (2) In Figure 8-8 another example of arbitration of packets with different priority is illustrated. Only router ports 1-5 are shown for clarity. At stage one input ports 1 and 3 have packets with logical addresses 80 and 52 respectively, which are both to be routed to output port 5.
  • Page 91 SpaceWire Router Addresses 80 – HIGH Priority 52 – LOW Priority Two packets waiting to use port 5 (Previous port which accessed port 5 = 4) Packet from port 1 completes HIGH priority packet from port 4 is selected Port number 3 waits Packet arrives on port 1 Packet from port 3 completes Packet waiting on port 1 is selected...

  • Page 92: Group Adaptive Routing

    8.3.3 Group Adaptive Routing The SpaceWire router routing table can be set up to support group adaptive routing of packets. Setting the routing table contents is described in section 9.3. In group adaptive routing a set of output ports can be assigned to a logical address. When a packet arrives with the logical address the routing table is checked for the set of output ports which the packet can use.

  • Page 93: Group Adaptive Routing When Ports Not Ready

    Address 76 – Routing table entry Header Deletion disabled Port 4 Port 5 Port 6 Group adaptive routing packet with address 76 arrives at port 1 Ports 4 and 5 are busy routing packet data from ports 2 and 3 Figure 8-11 Group adaptive routing when other ports busy 8.3.3.3 Group adaptive routing when ports not ready A similar arrangement to that of section 8.3.3.2 is shown in Figure 8-12.
  • Page 94 then a packet that that is addressed to go out of the same port that it arrived on will be discarded and a packet address error recorded. Command reply packets which are returned through the same port they arrived on are not affected by the value of the Enable Self-Addressing bit.

  • Page 95: Packet Blocking

    8.3.5 Packet Blocking The Time-Out Enable bit (bit 0) of the router control register enables the watchdog timers on the ports. When this bit is set and the watchdog timers are enabled the router is in “Watchdog Timer” mode. When it is clear and the watchdog timers are disable then the router is in the “Blocking Allowed”mode. In Blocking Allowed mode packets wait indefinitely on other packets to complete.
  • Page 96 In blocking allowed mode the network path is blocked until the destination node starts to accept data again. Packets waiting to use the network path will wait indefinitely. In watchdog timer mode the router will timeout and the network path will be cleared so other packets can use the path.
  • Page 97 Figure 8-16 Destination Node Blocked (c) Watchdog timer mode What happens when the routers are in Watchdog Timer mode and a destination becomes blocked is illustrated in Figure 8-17to Figure 8-20. Only SpaceWire ports 1 to 6 are shown for clarity. a) A packet arrives at port 3 of routing switch R1 destined for port 4 and then port 5 of R2 Figure 8-17 Destination Node Blocked: Watchdog Mode (a) b) The packet is routed towards its destination but during packet transfer the destination stalls...

  • Page 98: Stalled Source

    Figure 8-19 Destination Node Blocked: Watchdog Mode (c) d) The packet waiting at routing switch R1 port 2 is routed and the network blockage is cleared. Routing switch R2 port 5 still has data waiting to be sent followed by the end of packet, therefore packets routed to port 5 will again cause a blockage which will be cleared again in the same manner until the fault is detected by a higher level protocol.
  • Page 99 b) The packet from routing switch R1 port 3 is routed towards its destination but during packet transfer the source node stalls and does not supply any further data or the end of packet. c) The packet is blocked and the packet waiting at routing switch R1 port 2 cannot be routed. d) After an undetermined time the source node supplies the remaining data and end of packet and the packet waiting at R1-2 can be routed.
  • Page 100 Figure 8-25 Source Node Stalled: Watchdog Mode (a) b) The packet from routing switch R1 port 3 is routed towards its destination but during packet transfer the source node stalls and does not supply any more data or the end of packet. Figure 8-26 Source Node Stalled: Watchdog Mode (b) c) The packet is blocked and the packet waiting at routing switch R1 port 2 cannot be routed.

  • Page 101: Waiting For An Output Port

    8.3.5.3 Waiting for an output port When a packet arrives at an input port of the SpW-10X router is has to wait to be forwarded to an output port. How long the packet waits will depend on whether the router is in Blocking Allowed or Watchdog Timer mode and on what the output ports are doing.
  • Page 102 Packets can timeout and be spilled in a SpaceWire network without the destination receiving any notification of this. Packets with errors (e.g. parity error) can arrive at a destination terminated by an EEP. In a very special case it is also possible to receive an error free packet terminated by an EEP. It is important that the destination node is able to handle these cases.

  • Page 103: Register Definitions

    9. REGISTER DEFINITIONS This section describes the internal configuration registers of the SpW-10X Router. The following subsections contain register bit description tables which hold the following information: • The bit numbers of each field • A descriptive name for each field •...

  • Page 104: Register Addresses Summary

    registers allow the router management control and status information to be accessed by a network manager using configuration commands. Table 9-1 provides an overview of each of the different types of register within the configuration port. Each register type is then described in detail in the following subsections. Table 9-1 Types of Register within Configuration Port Register Name Description...

  • Page 105: Group Adaptive Routing Table Registers

    Table 9-2 Configuration Register Addresses Address 31–0 (0x0000 001F–0x0000 0000) 255–32 (0x0000 00FF –0x0000 0020) 256 (0x0000 0100) 257 (0x0000 0101) 258 (0x0000 0102) 259 (0x0000 0103) 260 (0x0000 0104) 261 (0x0000 0105) 262 (0x0000 0106) 263 (0x0000 0107) 264 (0x0000 0108) 265 (0x0000 0109) 9.3 GROUP ADAPTIVE ROUTING TABLE REGISTERS The Group Adaptive Routing (GAR) table is accessed through configuration memory addresses 32-...
  • Page 106 configuration memory address range of the GAR table is 32-255 (0x0000 0020 – 0x0000 00FF). The configuration memory address corresponds to the logical address; hence the GAR table entry at address 39 corresponds to logical address 39. The logical address to port mapping is held in the REQUEST field. Each bit in this field represents a physical output port;...
  • Page 107 Table 9-3 GAR Table Register Description Address Range: 32-255 (0x0000 0020 – 0x0000 00FF) Bits Name Reset Value RESERVED ‘0’ 10:1 REQUEST Undefined after power Unaltered by reset. 28:11 NOT USED DEL_HEAD Undefined after power Unaltered by reset. PRIORITY Undefined after power Unaltered by reset.

  • Page 108: Port Control/Status Registers

    Care must be taken when setting a the routing tables to avoid a possible infinite loop. For example if there is a SpaceWire link made between two ports of a single router and a logical address routes a packet out of one of these ports then that packet will arrive back at the router, and be routed back out of the port again.

  • Page 109: Configuration Port Control/Status Register Fields

    Bits Name Reset Value 28:24 Current port All bits connection set to one. 31:29 Port Type All bits set to zero. 9.4.2 Configuration port control/status register fields. The configuration port control/status fields specific to the configuration port are described in Table 9-5. Any errors occurring in the configuration port are reported via status bits in this register and the configuration command that caused the error is replied to with a NACK.
  • Page 110 Table 9-5 Configuration Port Control/Status Register Fields Bits Name Reset Value Error active ‘0’ Port timeout error ‘0’ Invalid Header ‘0’ Invalid Data CRC ‘0’ Invalid Destination ‘0’ Command not ‘0’ implemented Invalid Data Length ‘0’ Invalid RMW Data ‘0’ Length Invalid Destination ‘0’...
  • Page 111 Invalid Register ‘0’ Address Unsupported ‘0’ protocol error Source logical ‘0’ address error Not used ‘0’ Cargo too large ‘0’ Unused RMAP ‘0’ command or packet type 23:20 Not Used SpW-10X SpaceWire Router User Manual The invalid register address bit is set when an unknown register address is given in the command packet or a write is attempted to a read only register...

  • Page 112: Spacewire Port Control/Status Register Bits

    9.4.3 SpaceWire port control/status register bits. The port control/status fields specific to SpaceWire ports are shown in Figure 9-3 and Table 9-6. Figure 9-3 SpaceWire Port Control/Status Register Fields Note: Error status bits are cleared by writing to the Error Active register, see section 9.5.4. SpW-10X SpaceWire Router User Manual...
  • Page 113 Table 9-6 SpaceWire Port Control/Status Register Fields. Bits Name Reset Value Error active ‘0’ Packet ‘0’ address error Output port ‘0’ timeout error Disconnect ‘0’ error Parity error ‘0’ Escape error ‘0’ Credit error ‘0’ Character ‘0’ sequence error 10:8 Interface state “000”...
  • Page 114 Start ‘0’ Disable ‘0’ Deactivate ‘0’ 22:16 Transmitter Bits 18 to 16 are set data signalling according to the rate POR_TX_RATE(2:0) pins. (TXRATE) Bits 22:18 are set to zero. Not Used SpW-10X SpaceWire Router User Manual SpaceWire port will wait until the other end of the link tries to make a connection and will then automatically start.

  • Page 115: External Port Control/Status Register Bits

    9.4.4 External port control/status register bits. The port control/status fields specific to the External port are described in Table 9-7. Table 9-7 External Port Control/Status Fields Bits Name Reset Value Error Active ‘0’ Packet ‘0’ Address Error Output port ‘0’ timeout error Input Buffer...

  • Page 116: Router Identity Register

    Figure 9-4 Network Discovery Register Fields Table 9-8 Network Discovery Register Fields Bits Description Reset Value Device Type “0001” Return Port All bits set to zero 31:8 Ports in Run All bits state set to zero 9.5.2 Router Identity Register The router identity register address is 257 (0x0000 0101).

  • Page 117: Router Control Register

    Table 9-9 Router Identity Register Field Bits Description Reset Value 31:0 Router All bits set Identity to zero 9.5.3 Router Control Register The router control register address is 258 (0x0000 0102). The router control register sets various control bits in the SpaceWire router. Router functions which can be controlled are: •...
  • Page 118 Table 9-10 Router Control Register Fields Bits Name Reset Value Watchdog Set by the input signal Timer Mode POR_TIMEOUT_EN_N. / Blocking When ‘0’ – Watchdog Timer Mode Allowed Mode When ‘1’ – Blocking Allowed Mode Timeout Set by the input signal Selection POR_SEL_TIMEOUT0_N.
  • Page 119 Enable start Set by the input signal on request POR_START_ON_REQ_N. Enable Self Set by the input signal Addressing POR_ADDR_SELF_N 31:7 Not Used All bits set to zero SpW-10X SpaceWire Router User Manual the link using autostart or the link is started by configuration command then the port will not be disconnected on silence.

  • Page 120: Error Active Register

    The default timeout intervals of 60-80 µs or 1.3 ms are short. It may be necessary to increase the timeout interval by a configuration command writing to the router control register. When initially prototyping a SpaceWire system it is advisable to set the timeout interval to 1.3 s and then decrease it to an appropriate value once basic system operation has been established.

  • Page 121: Time-Code Register

    Table 9-11 Error Active Register Fields Bits Name Reset Value Configuration Port ‘0’ Error Active 30:1 SpaceWire and All bits External Port Error set to Active zero Not used All bits set to zero 9.5.5 Time-Code Register The time-code register address is 260 (0x0000 0104). The time-code register contains the current value of the internal time-code register.

  • Page 122: Device Manufacturer And Chip Id Register

    Bits Name Time Value Time-Code Flags 31:8 Not used 9.5.6 Device Manufacturer and Chip ID Register The device manufacturer and chip ID register address is 261 (0x0000 0105). This register contains three eight-bit fields which hold a device manufacturer identity, chip identity and version number.

  • Page 123: General Purpose Register

    9.5.7 General Purpose Register The general purpose register address is 262 (0x0000 0106). The general purpose register contains 32-bits and may be set by a configuration write command to a user defined value as required. It may also be read with a configuration read command. The general purpose register has no effect on the operation of the router.

  • Page 124: Transmit Clock Control Register

    Table 9-14 Time-Code Enable Register Fields Bits Name Reset Value Reserved SpaceWire Time-Code Enable External Time- Code Interface Enable 11:10 Not Used All bits set to zero Time-code Flag Mode 31:13 Not used All bits set to zero 9.5.9 Transmit Clock Control Register The transmit clock control register address is 264 (0x0000 0108).
  • Page 125 If a SpaceWire port that is being used to configure a router has its transmit clock turned off then it will not be possible to configure the router using that port. Unless there is another connection with an active clock and which is not disabled that can be used to perform configuration the router will have to be reset before it can be configured again.
  • Page 126 Table 9-15 Transmit Clock Control Register Bits Bits Name Reset Value TXDIV “01” Not used All bits set to zero 15:8 Enable clock All bits set to 1 20:16 Tx10MbitDIV Dependent on FEEDBDIV at reset FEEDBDIV=“000” “00100” FEEDBDIV=“001” “00101” FEEDBDIV=“010” “00110”...

  • Page 127: Destination Key Register

    9.5.10 Destination Key Register The Destination Key register address is 265 (0x0000 0109). The destination key register fields are listed in the table below. Bits Name Reset Value DESTKEY 31:8 Not used All bits set to zero 9.5.11 Unused Registers and Register Bits If an unused register address is referenced in a configuration command then the command will not be acted upon and a NACK will be sent in the reply to the command.

  • Page 128: Switching Characteristics

    10. SWITCHING CHARACTERISTICS 10.1 CLOCK AND RESET TIMING PARAMETERS The global clock and asynchronous reset timing parameters are listed below. Table 10-1 Clock and reset timing parameters Description Clock period minimum value Clock period maximum value Clock minimum pulse width Clock input jitter PLL lock time after reset Reset minimum pulse width...

  • Page 129: External Port Timing Parameters

    Table 10-2 Serial signal timing parameters Description DS maximum input bit rate DS minimum consecutive edge separation Minimum edge separation between 2 consecutive edges Data Strobe output skew & jitter (incl. LVDS driver) 10.3 EXTERNAL PORT TIMING PARAMETERS The external port input timing parameters can be viewed below EXT_IN_WRITE_N EXT_IN_DATA EXT_IN_FULL_N...

  • Page 130: Time-Code Interface Timing Parameters

    Table 10-3 External port timing parameters Description Write enable setup time to CLK rising edge Write enable hold time after CLK rising edge Write data setup time to CLK rising edge Write data hold time after CLK rising edge CLK rising edge to full flag output CLK rising edge to full flag output Read enable setup time to CLK rising edge Read enable hold time after CLK rising edge...

  • Page 131: Error/Status Interface Timing Parameters

    EXT_TICK_OUT EXT_TIME_OUT Figure 10-5 Time-Code Output Interface TIME_CTR_RST Figure 10-6 Time-code TIME_CTR_RST interface The Time-code timing parameters are shown below. Table 10-4 Time-code interface timing parameters Description Tick-in and time reset low time Tick-in and time reset high time Select external time and Time-code in set-up time Select external time and Time-code in hold time Tick-out low time Tick-out high time...
  • Page 132 Table 10-5 Status Multiplexer timing parameters Description Status address change to status output change CLK rising edge to status output SpW-10X SpaceWire Router User Manual Symbol STMUX CLKSTMUX Preliminary Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: July 2008 Value Units 3 to 20 5 to 25...

  • Page 133: Latency And Jitter

    10.6 LATENCY AND JITTER The timing parameters for the data and time-code latency and the time-code jitter are derived from the receive clock, transmit clock and system clock period. The worst case number of clock cycles required is used in each equation. In the SpaceWire router the system clock is a known frequency and the transmitter and receiver frequency are derived from the input and output bit rates.

  • Page 134: Time-Code Latency

    SpaceWire port to SpaceWire port Last bit of data into receiver to last bit of data out of transmitter (Worst case where transmitter is sending a time-code and FCT character before data) × × SSDATA RXPERIOD SpaceWire port to External port Last bit of data into receiver to external port not empty flag ×...

  • Page 135: Time-Code Jitter

    10.6.5 Time-code Jitter The variation in time to propagate a time-code through a routing switch. Time-code jitter occurs in the synchronisation handshaking circuits and the transmitter where the maximum delay time the time-code has to wait to be transmitted is one data character. The jitter is measured as ×...

  • Page 136: Electrical Characteristics

    11. ELECTRICAL CHARACTERISTICS The electrical characteristics for the SpaceWire router are defined in this section 11.1 DC CHARACTERISTICS The operating conditions are listed in Table 11-1. For a detailed list of the operating conditions see [AD3]. Symbol Supply voltage Ambient temperature Static power (CLK input is static, after reset) Total OFF power (static and dynamic): Reset active power consumption (CLK input with 30 MHz signal,...

  • Page 137: Absolute Maximum Ratings

    371k Atmel MH1RT sites (approximately 285k gates) Temperature Application dependent Package QFP196 with 25 mil pin spacing Environment Application dependent Learning factor Established Atmel ASIC technology (MH1RT) for several years SpW-10X SpaceWire Router User Manual Description Table 11-3 Reliabilty Information Preliminary Ref.:...

  • Page 138: Application Guidelines

    12. APPLICATION GUIDELINES In this section an example circuit diagram is provided and PCB and design guidelines presented.; 12.1 EXAMPLE CIRCUIT DIAGRAM A schematic showing how the SpW-10X device should be connected is provided on the following page. This is a complete schematic for a stand-alone router except for the 3.3V power supply and reset signal.

  • Page 139: Spacewire Router

    SpW-10X SpaceWire Router User Manual Preliminary Ref.: UoD_SpW-10X_ UserManual Issue: 3.4 Date: July 2008...

  • Page 140: Pcb Design And Layout Guidelines

    12.2 PCB DESIGN AND LAYOUT GUIDELINES PCB design and layout guide lines are provided in this section. 12.2.1 CLK 1. Series termination should be used on the CLK signal. 2. Stubs on the CLK signal shall not be used. 3. Guard tracks shall be provided around the CLK signal trace connected to the ground plane approximately every 1 cm.

  • Page 141: External Ports

    2. LVDS fail safe resistors need not be adjacent to the termination resistor. Their location is not critical but the stub lengths to the termination resistors should be less than 20 mm. 3. LVDS tracks shall be 100 ohm differential impedance. 4.

  • Page 142: Pll

    12.2.10 PLL See Figure 12-1 the internal wiring of PLL block to better understand the external board recommended layout. The Voltage drop between PLL loop filter (LF) and the PVCOBIAS pads will be converted into a current (Ivco) which will determine the VCO frequency. It is critical to avoid any disturbance of that voltage drop at this will translate directly to jitter in the VCO frequency.

  • Page 143: Anomalies And Warnings

    13. ANOMALIES AND WARNINGS In this section a list of anomalies and warnings is provided: 13.1 ANOMALIES The following anomalies are present in the prototype SpW-10X router device: 1. Simultaneous transitions on data and strobe can occur during reset and power up. This may be a problem when operating with legacy IEEE-1355 devices but is not a problem when operating with SpaceWire compliant devices.
  • Page 144 The deactivate mode (see also section 9.4.3) does not tri-state the LVDS outputs. The LVDS outputs are cold-sparing and when disabled both outputs in an LVDS differential pair are pulled up to 3.3V and have an impedance of the order of 1 kohm. Since they are differential outputs and are both are at the same voltage no current will flow.

  • Page 145: Reset Anomaly

    Packets can timeout and be spilled in a SpaceWire network without the destination receiving any notification of this. Packets with errors (e.g. parity error) can arrive at a destination terminated by an EEP. In a very special case it is also possible to receive an error free packet terminated by an EEP. It is important that the destination node is able to handle these cases.
  • Page 146 set a glitch may occur on data and strobe, see Figure 13-3. A simultaneous transition or glitch on data and strobe may occur when reset is released, Figure 13-4. Figure 13-2 Reset Waveform with Data and Strobe Both High Figure 13-3 Glitches on Data or Strobe during Reset Figure 13-4 Simultaneous Transition of Data and Strobe during Reset SpW-10X SpaceWire Router...

  • Page 147: Data Strobe Disable Waveform

    SpaceWire compliant SMCS332SpW and SMCS116SpW devices, which are or shortly will be available from Atmel. If operation with legacy units which use IEEE-1355 devices is necessary and these devices cannot be replaced by the new SpaceWire compliant parts, then the following reset sequence is recommended: 1.

  • Page 148: Parity Error Anomaly

    13.4 PARITY ERROR ANOMALY 13.4.1 Parity Error Action A parity error on the SpaceWire link causes the link to be disconnected by the SpaceWire router. If a packet is being received the packet is discarded and an error end of packet (EEP) is appended to the end of the packet.

  • Page 149: Parity Error Workaround

    Figure 13-7 No error end of packet inserted after parity error 13.4.3 Parity Error Workaround There is no specific workaround for this anomaly as a similar situation can occur in any case when an error on a link does not cause an immediate parity error but one is produced in a subsequence character.

  • Page 150: Technical Support

    Technical support for the SpW-10X Router is provided by STAR-Dundee Ltd. A range of SpW-10X evaluation boards is available along with other test equipment, cables etc. See for details. Technical support is provided by STAR-Dundee. All requests for support should be submitted to the Atmel support hotline: Email: assp-applab.hotline@nto.atmel.com SpW-10X...

  • Page 151: Document Changes

    Correction made to support email address. 15.3 ISSUE 3.1 TO ISSUE 3.2 Section Change Table 1-2 RD3 added “Atmel MH1RT Cold Sparing I/O Buffers”. Figure 3.1 Text in diagram change from “non-blocking crossbar switch” to “crossbar switch”. Explanation of “non-blocking” nature of crossbar switch added.

  • Page 152: Issue 3.0 To Issue 3.1

    5.7.4 VCO bias resistor value corrected (Section 5.7.4). 8.1.5 Tri-state mode changed to deactivate mode. Calculation of deactivated power consumption added. 9.4.3 Table 9-6 Tri-state mode changed to deactivated mode. 9.5.8 Description for ‘time-code flag mode bit’ added. 11.1 Table 11-1 Power information updated.

  • Page 153: Issue 2.4 To Issue 2.5

    15.7 ISSUE 2.3 TO ISSUE 2.4 Section Change Title Change from data sheet to user manual Title Add Atmel part number as a reference External Ports Add depth of external port FIFOs. SpaceWire Rename data strobe IOs so the naming is consistent in the Signals document.

  • Page 154: Issue 2.1 To Issue 2.2

    15.9 ISSUE 2.1 TO ISSUE 2.2 Section Change ASIC pin locations 15.10 ISSUE 2.0 TO ISSUE 2.1 Section Change 15.11 ISSUE 1.7 TO ISSUE 2.0 Section Change Final updates and editorial corrections before release 15.12 ISSUE 1.6 TO ISSUE 1.7 Section Change Corrections added following validation...
  • Page 155 15.17 ISSUE 1.1 TO ISSUE 1.2 Section Change 6.3, 6.4, 6.5 Table 6-3, FPGA timing data added Table 6-4, Table 6-5 15.18 ISSUE 1.0 TO ISSUE 1.1 Section Change Table 5-1 FEEDBDIV PLL clock settings section added Table 5-5 STAT_MUX_OUT changed to multi function pin Table 5-6 Power on reset signals mapped to STAT_MUX_OUT pins 8.1.6...

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