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43 GND
44 GND
45 GND
46 GND
47 N.C.
48 VCC
49 VCC
50 VCC
51 VCC
Note (1) LVDS connector pin order defined as follows.
Note (2) Reserved for internal use. Please leave it open.
Note (3) Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
Note (4) LVDS signal pin connected to the LCM side has the following diagram. R1 in the system side should be
less than 1K Ohm. (R1 < 1K Ohm)
Selector (pin7)
System side
System side
Note (5) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
Ground
Ground
Ground
Ground
No Connection
Power input (+12V)
Power input (+12V)
Power input (+12V)
Power input (+12V)
R2
R2
R1
R1
- 13 -
TCON
TCON
Setting
Setting
R3
R3
LCM side
LCM side
(2)
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