LG 39LB5600 Service Manual page 37

+1.5V_DDR
CLose to DDR3
DDR_SAMSUNG
IC1201-*1
K4B1G1646G-BCK0
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A10/AP
R7
A11
N7
A12/BC
T3
A13
M7
NC_5
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CKE
L2
CS
K1
ODT
J3
RAS
K3
CAS
L3
WE
T2
RESET
F3
DQSL
G3
DQSL
C7
DQSU
B7
DQSU
E7
DML
D3
DMU
E3
DQL0
F7
DQL1
F2
DQL2
F8
DQL3
H3
DQL4
H8
DQL5
G2
DQL6
H7
DQL7
D7
DQU0
C3
DQU1
C8
DQU2
C2
DQU3
A7
DQU4
A2
DQU5
B8
DQU6
A3
DQU7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
+1.5V_DDR
A-MVREFDQ A-MVREFCA
CLose to Saturn7M IC
M8
VREFCA A-MVREFCA
H1
VREFDQ A-MVREFDQ
L8
ZQ
+1.5V_DDR
B2
VDD_1
D9
10V 10uF C1205
VDD_2
G7
10V 10uF C1227
VDD_3
K2
C1207 0.1uF
VDD_4
K8
C1208 0.1uF
VDD_5
N1
C1210 0.1uF
VDD_6
N9
C1211 0.1uF
VDD_7
R1
C1212 0.1uF
VDD_8
R9
C1213 0.1uF
VDD_9
C1214 0.1uF
C1215 0.1uF
A1
VDDQ_1
A8
VDDQ_2
C1
VDDQ_3
C9
VDDQ_4
D2
VDDQ_5
E9
VDDQ_6
F1
VDDQ_7
H2
VDDQ_8
H9
VDDQ_9
J1
NC_1
J9
NC_2
L1
NC_3
L9
NC_4
T7
A-MA14
NC_6
A9
VSS_1
B3
VSS_2
E1
VSS_3
G8
VSS_4
J2
VSS_5
J8
VSS_6
M1
VSS_7
M9
VSS_8
P1
VSS_9
P9
VSS_10
T1
VSS_11
T9
VSS_12
B1
VSSQ_1
B9
VSSQ_2
D1
VSSQ_3
D8
VSSQ_4
E2
VSSQ_5
E8
VSSQ_6
F9
VSSQ_7
G1
VSSQ_8
G9
VSSQ_9
+1.5V_DDR
DDR_HYNIX
IC1201
H5TQ1G63EFR-PBC
EAN61829003
M8 N3
VREFCA A0 A-MA0
P7
A-MA1
A1
P3
A2 A-MA2
H1 N2
VREFDQ A3 A-MA3
P8
A4 A-MA4
P2
A5 A-MA5
R1203
L8 R8
A-MA6
ZQ A6
R2
240
A7 A-MA7
1% T8
A-MA8
A8
B2 R3
VDD_1 A9 A-MA9
D9 L7
A-MA10
VDD_2 A10/AP
G7 R7
VDD_3 A11 A-MA11
K2 N7
A-MA12
VDD_4 A12/BC
K8 T3
VDD_5 NC_7 A-MA13
N1
VDD_6
N9 M7
VDD_7 NC_5
R1
VDD_8
R9 M2
VDD_9 BA0 A-MBA0 A-MCK
N8
BA1 A-MBA1
M3
A-MBA2
BA2
A1 C1209
VDDQ_1
A8 J7
0.01uF
VDDQ_2 CK
C1 K7 50V
VDDQ_3 CK
C9 K9
A-MCKE
VDDQ_4 CKE
D2
VDDQ_5 A-MCKB
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT A-MODT
H2 J3 +1.5V_DDR
VDDQ_8 RAS A-MRASB
H9 K3
VDDQ_9 CAS A-MCASB
R1231
L3
10K
WE A-MWEB
J1
NC_1
J9 T2
NC_2 RESET A-MRESETB
L1
NC_3
L9
NC_4
T7 F3
A-MDQSL
NC_6 DQSL
G3
DQSL A-MDQSLB
C7
A9
VSS_1 DQSU A-MDQSU
B3 B7
A-MDQSUB
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML A-MDML
J2 D3
VSS_5 DMU A-MDMU
J8
VSS_6
M1 E3
A-MDQL0
VSS_7 DQL0
M9 F7
VSS_8 DQL1 A-MDQL1
P1 F2
A-MDQL2
VSS_9 DQL2
P9 F8
VSS_10 DQL3 A-MDQL3
T1 H3
A-MDQL4
VSS_11 DQL4
T9 H8
VSS_12 DQL5 A-MDQL5
G2
A-MDQL6
DQL6
H7
DQL7 A-MDQL7
B1
VSSQ_1
B9 D7
VSSQ_2 DQU0 A-MDQU0
D1 C3
VSSQ_3 DQU1 A-MDQU1
D8 C8
VSSQ_4 DQU2 A-MDQU2
E2 C2
VSSQ_5 DQU3 A-MDQU3
E8 A7
A-MDQU4
VSSQ_6 DQU4
F9 A2
VSSQ_7 DQU5 A-MDQU5
G1 B8
A-MDQU6
VSSQ_8 DQU6
G9 A3
VSSQ_9 DQU7 A-MDQU7
IC101
MSD804KKX
A11 B23
A-MA0 A_DDR3_A[0] SYMBOL.B B_DDR3_A[0]
C14 D25
A-MA1
A_DDR3_A[1] B_DDR3_A[1]
B11 F22
A-MA2 A_DDR3_A[2] B_DDR3_A[2]
F12 G22
A-MA3 A_DDR3_A[3] B_DDR3_A[3]
C15 E24
A-MA4 A_DDR3_A[4] B_DDR3_A[4]
E12 F21
A-MA5 A_DDR3_A[5] B_DDR3_A[5]
A14 E23
A-MA6
A_DDR3_A[6] B_DDR3_A[6]
D11 D22
A-MA7 A_DDR3_A[7] B_DDR3_A[7]
B14 D24
A-MA8
A_DDR3_A[8] B_DDR3_A[8]
D12 D21
A-MA9 A_DDR3_A[9] B_DDR3_A[9]
C16 C24
A-MA10
A_DDR3_A[10] B_DDR3_A[10]
C13 C25
A-MA11 A_DDR3_A[11] B_DDR3_A[11]
A15 F23
A-MA12
A_DDR3_A[12] B_DDR3_A[12]
E11
E21
A-MA13 A_DDR3_A[13] B_DDR3_A[13]
B13 D23
A-MA14
A_DDR3_A[14] B_DDR3_A[14]
F13 G20
A-MBA0 A_DDR3_BA[0] B_DDR3_BA[0]
B15 F24
A-MBA1 A_DDR3_BA[1] B_DDR3_BA[1]
E13 F20
A-MBA2
A_DDR3_BA[2] B_DDR3_BA[2]
C17 G25
A-MCK
A_DDR3_MCLK B_DDR3_MCLK
A17 G23
A-MCKB A_DDR3_MCLKZ B_DDR3_MCLKZ
B16 F25
A-MCKE
A_DDR3_MCLKE B_DDR3_MCLKE
E14 D20
A-MODT A_DDR3_ODT B_DDR3_ODT
B12 B25
A-MRASB A_DDR3_RASZ B_DDR3_RASZ
A12 B24
A-MCASB A_DDR3_CASZ B_DDR3_CASZ
C12 A24
A-MWEB A_DDR3_WEZ B_DDR3_WEZ
F11 E20
A-MRESETB A_DDR3_RESET B_DDR3_RESET
B19 K24
A-MDQSL
A_DDR3_DQSL B_DDR3_DQSL
C18 K25
A-MDQSLB A_DDR3_DQSLB B_DDR3_DQSLB
B18 J21
A-MDQSU A_DDR3_DQSU B_DDR3_DQSU
A18 J20
A-MDQSUB
A_DDR3_DQSUB B_DDR3_DQSUB
E15 H24
A-MDML A_DDR3_DQML B_DDR3_DQML
A21 L20
A-MDMU A_DDR3_DQMU B_DDR3_DQMU
D17 L23
A-MDQL0
A_DDR3_DQL[0] B_DDR3_DQL[0]
G15 J24
A-MDQL1 A_DDR3_DQL[1] B_DDR3_DQL[1]
B21 L24
A-MDQL2
A_DDR3_DQL[2] B_DDR3_DQL[2]
F15 J23
A-MDQL3 A_DDR3_DQL[3] B_DDR3_DQL[3]
B22 M24
A-MDQL4
A_DDR3_DQL[4] B_DDR3_DQL[4]
F14 H23
A-MDQL5 A_DDR3_DQL[5] B_DDR3_DQL[5]
A22 M23
A-MDQL6
A_DDR3_DQL[6] B_DDR3_DQL[6]
D15 K23
A-MDQL7 A_DDR3_DQL[7] B_DDR3_DQL[7]
G16 G21
A-MDQU0 A_DDR3_DQU[0] B_DDR3_DQU[0]
B20 L22
A-MDQU1 A_DDR3_DQU[1] B_DDR3_DQU[1]
F16 H22
A-MDQU2 A_DDR3_DQU[2] B_DDR3_DQU[2]
C21 K20
A-MDQU3 A_DDR3_DQU[3] B_DDR3_DQU[3]
E16 H20
A-MDQU4
A_DDR3_DQU[4] B_DDR3_DQU[4]
A20 L21
A-MDQU5 A_DDR3_DQU[5] B_DDR3_DQU[5]
D16 H21
A-MDQU6
A_DDR3_DQU[6] B_DDR3_DQU[6]
C20 K21
A-MDQU7 A_DDR3_DQU[7] B_DDR3_DQU[7]
NC4_S7LRM
M1_DDR (1DDR)
2012/06/21
54
LGE Internal Use Only