Sharp LC-32DH57E-BK Service Manual page 72

LC-32DH57E-BK/RU-BK/S-BK
2.10.2 Pin Connections and short description
Pin No. Pin Name
29-44 IO0-IO7
16 CLE
17 ALE
9 CE#
18 WE#
8 RE#
19 WP#
7 A/B#
37 VCC
36 VSS
1-6, 10-11, 14-15, NC
20-28, 33-35,
39-40, 45-48
2.11. IC8455 (VHiBR24S64F-1Y)
This IC is a block diagram and description LC-32A47E/RU/V (S59Z4LC32A47E) please see the service manual.
I/O
I/O DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read/program opera-
tions.
The inputs are latched on the rising edge of Write Enable (WE#).
The I/O buffer float to High-Z when the device is deselected or the outputs are disabled.
I COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write
Enable (WE#).
I ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write
Enable (WE#).
I CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect the
memory.
I WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge
of WE#.
I READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE# which also increments the internal column address counter by one.
I WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program/erase)
operations.
I READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
— SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
— GROUND
— NO CONNECTION
Pin Function
5 – 16