Yamaha RX-V463 Service Manual page 48

RX-V463/HTR-6140/DSP-AX463
Pin No. Function Name
1 RXOUT
2 RX0
3 RX1
4 RX2
5 RX3
6 DGND
7 DVDD
8 RX4
9 RX5
10 RX6
11 DVDD
12 DGND
13 LPF
14 AVDD
15 AGND
16 RMCK
17 RBCK
18 DGND
19 DVDD
20 RLRCK
21 RDATA
22 SBCK
23 SLRCK
24 SDIN
25 DGND
26 DVDD
27 XMCK
28 XOUT
29 XIN
30 DVDD
31 DGND
32 EMPHA/UO/CD
33 AUDIO/VO
34 CKST/PT
35 INT
36 RERR
37 DO
38 DI
39 CE
40 CL
41 XMODE
42 DGND
43 DVDD
44 PIO0
45 PIO1
46 PIO2
47 PIO3
48 PIOEN
1) Withstand voltage input/output: I or O = -0.3 to 3.6 V, Is = -0.3 to 5.5 V
2) Pins 32 and 33 are input pins for chip address setting, when pin 41 = "L".
3) Pin 34 is a demodulation function master or an input pin for slave setting, when pin 41 = "L".
4) Pin 35 is a modulation function or an input pin for general-purpose I/O function switch setting, when pin 41 = "L".
5) ON/OFF for all power supplies must be done at the same timing as a latch-up countermeasure.
48
I/O
O Output pin of input bi-phase selection data
Is Input pin of TTL-compatible digital data
I Digital data input pin with built-in amplifier that supports coaxial
Is Input pin of TTL-compatible digital data
Is Input pin of TTL-compatible digital data
Digital GND
Digital power supply (3.3 V)
Is Input pin of TTL-compatible digital data
Is TTL-compatible digital data / Validity flag input pin for modulation
Is TTL-compatible digital data / User data input pin for modulation
Digital power supply for PLL
Digital GND for PLL
O PLL loop filter connection pin
Analog power supply for PLL (3.3 V)
Analog GND for PLL
O R system clock output pin (256 fs, 512 fs, XIN, VCO)
O/I R bit clock input/output pin (64 fs)
Digital GND
Digital power supply (3.3 V)
O/I R LR clock input/output pin (fs)
O Output pin of serial audio data
O S bit clock output pin (32 fs, 64 fs, 128 fs)
O S LR clock output pin (fs/2, fs, 2 fs)
Is Input pin of serial audio data
Digital GND
Digital power supply (3.3 V)
O Oscillation amplifier output pin
O Quartz resonator connection output pin
I Quartz resonator connection, input pin of external supply clock (24.576 MHz or 12.288 MHz)
Digital power supply (3.3 V)
Digital GND
I/O Emphasis information / U data output / C data output / Chip address setting pin
I/O Non-PCM detection / V flag output / Chip address setting pin
I/O Output of clock switch transitional period signal / Preamble B output / Demodulation master or slave
function switch pin
I/O Interrupt output for microprocessor (Possible to select an interrupt factor.) / Modulation or general-
purpose I/O switch pin
O PLL clock error, data error flag output
O Microprocessor I/F, read data output pin (3-state)
Is Microprocessor I/F, write data input pin
Is Microprocessor I/F, chip enable input pin
Is Microprocessor I/F, clock input pin"
Is System reset input pin
Digital GND
Digital power supply (3.3 V)
O
Sport input select
O
O Audio direct stereo ON
O Audio clock select
I/O Modulation data output / General-purpose I/O enable output pin
Detail of Function
(No connected.)
(No connected.)