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BDL5531EL LCD
Audio input - Sensitivity 500mVrms, the amplifier outputs full power when the input level reaches
500mVrms, terminated with impedance >10k .
Lineout output - Stereo, 2Vrms output.
Speaker output - 2 x 12 Wrms back firing speakers, with T.H.D. < 10%.
2.2.2
AV input signal requirements
CVBS input -1000mVpp (including 300 mV sync level), terminated with input impedance of 75 .
S-Video input - Y: 1000mVpp, C: 300mVpp, terminated with input impedance of 75 .
Component video input - Y: 1000mVpp, PbPr: ±350mVpp, terminated with input impedance
HD ready - HD ready logo not required, but requirements to be fulfilled as-Display, display
The minimum native resolution of the display or display engine is 720 physical lines in
wide aspect ratio.
Video Interfaces:
The display device accepts HD input via:
Analog YPbPr. "HD ready" displays support analog YPbPr as a HD input format to allow
full compatibility with today's HD video sources in the market. Support of the YPbPr
signal should be through common industry standard connectors directly on the HD ready
display or through an adaptor easily accessible to the consumer; and:
HDMI HD capable inputs accept the following HD video formats:
1280x720 @ 50 and 60Hz progressive scan ("720p")
1920x1080 @ 50 and 60Hz interlaced ("1080i")
The HDMI input supports copy protection (HDCP).
FHD- FHD ready logo not required, but requirements to be fulfilled as: 1080p/50, and 1080p/60.
HDMI Input - Compliance with HDMI Specification 1.3 or later, 480i/p, 576i/p, 720p, 1080i/p
signal handling capability.
TMDS channel:
DDC channel:
General Product Specification
of 75 . 480i/p, 576i/p, 720p, 1080i/p signal handling capability.
engine:
Carries audio, video and auxiliary data.
Signaling method: According to HDMI Ver. 1.3b specification. (Type A
HDMI).
Video pixel rate: 25 MHz to 165 MHz (Type A)
Pixel encodings: RGB 4:4:4, YCbCr 4:2:2, YCbCr 4:4:4.
Audio sample rates: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96kHz,
176.4 kHz, 192 kHz.
Audio channels: up to 8.
Allows source to interrogate capabilities of sink.
I²C signaling with 100 kHz clock.
E-EDID data structure according to EIA/CEA-861B and VESA
Enhanced EDID.
Content protection:
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