LG 49UF6430 Service Manual page 53

IC12800
LGE5352(URSA11)
AD26
URSA_RESET
PAD_RESET
PAD_I2C_HSC_SDA/[VSYNC_LIKE_SPI2]
AH4
XIN_URSA
PAD_XOUT PAD_I2C_HSC_SCL/[VSYNC_LIKE_SPI3]
AH3
XO_URSA PAD_XIN
AE9
I2CS_SDA PAD_I2C_S_SDA
AR13200
AD9
I2CS_SCL 33 PAD_I2C_S_SCL
C13200 C13201
AD10
56pF 56pF
PAD_I2C_M_SDA
AE10
50V 50V
PAD_I2C_M_SCL/[VSYNC_LIKE_SP1]
OPT
OPT
URSA_UART2_TX
E8
PAD_GPIO00/[UART2_TX]
F7
PAD_GPIO01/[UART2_RX]
URSA_UART2_RX
E7
PAD_GPIO02/[UART1_TX]
OPT OPT OPT
F6
URSA_UART1_TX
PAD_GPIO03/[CHIP_VDET]
0.01uF 0.01uF 0.01uF
25V 25V 25V
C13217 C13218 C13219
AD27
SPI_CZ PAD_SPI_CZ
R14402 33
AC27
SPI_CK PAD_SPI_CK
R14403 33 AC28
SPI_DI PAD_SPI_DI
AC26
SPI_DO PAD_SPI_DO
AE25
PAD_INTERUPT_R21
AD25
PAD_INTERUPT_R20
URSA_UART1_RX
OPT
0.01uF
D7
25V
PAD_IRE/[UART1_RX]
C13220
R13211 0
AC25
PAD_TESTPIN
AC9
GND_EFUSE
R13212 0
R13200 10K
OPT AC19
GPIO[09]
R13201 10K AD19
OPT
GPIO[08] PAD_TCON10/[HDMI_R_DDC_CLK3]
AC18
VID1 GPIO[07] PAD_TCON11/[HDMI_R_DDC_DAT3]
PAD_TCON12/[HDMI_R_HP3]
AE19
VID0 GPIO[06] PAD_TCON13/[HDMI_R_CEC3]
PAD_TCON14/[HDMI_T_CEC]
AD7
R13202 33
OPT GPIO[64] PAD_TCON15/[HDMI_T_HPD]
AE7
R13203 33
OPT GPIO[65]
AC7
R13204 33
OPT GPIO[66]
AD8
R13205 33
OPT GPIO[67]
AC8
R13206 33
OPT GPIO[63]
PAD_GPIO12/[VX1_RX_HTPD_O]
PAD_GPIO13/[VX1_RX_HTPD_V]
M4
R13207 33
OPT GPIO[70]
M5
R13208 33
OPT GPIO[72] PAD_GPIO15/[VX1_RX_LOCK_O]
N4
R13209 33
OPT GPIO[73] PAD_GPIO16/[VX1_RX_LOCK_V]
N5
R13210 33
OPT GPIO[71]
AE6
NC_1
AD6
NC_2
URSA Option
Low High
URSA_OPT_0 Rx_Vx1 Rx_LVDS
URSA_OPT_6
OS_Moudule LGD_Module
URSA_OPT_1
URSA_OPT_5
URSA_OPT_4 PRINT_ON PRINT_OFF URSA_OPT_4
Div_BIT0
URSA_OPT_5 Reserverd Reserverd
Div_BIT1
URSA_OPT_6 Reserverd Reserverd
URSA_OPT_0
URSA_OPT_1
BIT [2/1/0] Tx Lane
0/0/0 4K@120 (4 DDR)
0/0/1 4k@60 (2 DDR)
0/1/0 4K@120 8K(98UF8K 4DDR)
OLED 4K@120(4 DDR)
0/1/1
1/0/0 FHD@120 (4 DDR)
1/0/1 FHD@60 (2 DDR)
FHD@60 (4 DDR)
1/1/0
Reserved
1/1/1
4K@60(4 DDR)
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright 2015 LG Electronics Inc. All rights reserved.
Only for training and service purposes
AD11
AC10
AC23
URSA_OPT_0
PAD_SPI1_CK/GPIO58
AD24
PAD_SPI1_DI/GPIO59 Div_BIT0
AD23
Div_BIT1
PAD_SPI2_CK/GPIO56
AC22
URSA_L/D_ctrl
PAD_SPI2_DI/GPIO57 URSA_OPT_4
R13228 33
AE24
L/D_CLK
PAD_SPI3_CK/GPIO54
AE22 URSA_L/D_ctrl R13229 33
PAD_SPI3_DI/GPIO55 L/D_DI
AD22
PAD_SPI4_CK/GPIO52 URSA_OPT_5
AC21
PAD_SPI4_DI/GPIO53 URSA_OPT_6
URSA_L/D_ctrl
AC24 R13215 33
L/D_VSYNC
PAD_VSYNC_LIKE/GPIO40
C13214 C13215
C13216
5pF 5pF
5pF +3.3V_NORMAL
50V 50V
AE13 DIM0 50V
PAD_DIM00/GPIO32
AD13 DIM1 OPT
PAD_DIM01/GPIO33
R13226
AC13 DIM2
PAD_DIM02/GPIO34 10K
AE15
PAD_DIM03/GPIO35
AC14
PAD_DIM04/GPIO36 URSA_OPT_1
R13227
AD14
URSA_BIT0 10K
PAD_DIM05/GPIO37
AD15
URSA_BIT1
PAD_DIM06/GPIO38
AC15
PAD_DIM07/GPIO39 URSA_BIT2 FRC_FLASH_WP
E4
PAD_TCON0/STV2
D5
PAD_TCON1/OE
E6
PAD_TCON2/YV1C
E5
PAD_TCON3/CPV
F5
PAD_TCON4/STV1
F4
PAD_TCON5/SFT
D6
PAD_TCON6/TPV
D4
PAD_TCON7/POL
AC4
PAD_TCON8/[VX1T_HTPDN]
AD4
PAD_TCON9/[VX1T_LOCKN]
AA4
AB5
AB4
AA5
AD5
AE5
AD21
PAD_GPIO04 Data_Format_1
AD20
Data_Format_0
PAD_GPIO05
AC6
0.01uF 0.01uF
GPIO[74]
AC5 25V 25V
GPIO[75] C13202 C13205
AB7
GPIO[76]
AB6
GPIO[69]
AE21
PAD_GPIO10
AC20
PAD_GPIO11 URSA_RX_Vx1_HTPDn
AE12
R13218 10K
URSA_RX_Vx1_HTPDn
AD12
R13219 10K
AD18
PAD_GPIO14
AC11
AC12
AE18
PAD_GPIO17
B1
NC_3
AG1
NC_4
AH2
NC_5
AH27
NC_6
B28
C13204 C13203 C13213 C13206
NC_7
AG28 0.01uF 0.01uF 0.01uF
0.01uF
NC_8
25V 25V 25V 25V
+3.3V_NORMAL
Reserved
Reserved
Division Type
Rx Interface
Module Type
URSA_BIT0
Tx Lane
URSA_BIT1
URSA_BIT2
BIT [1/0] Module Division
0/0 Non Division
0/1 2 Division
1/0 4 Division
1/1 8 Division
SPI Flash
URSA11_SERIAL_FLASH_MEMORY_MXIC(MAIN)
MX25L3235E
MACRONIX INTERNATIONAL CO., LTD.
CS
1
SPI_CZ
R13245 SO/SIO1
33
2
SPI_DO
FLASH_WP_URSA
WP/SIO2
1K
R13244
3
+3.3V_NORMAL
U_SPI_WP_f_URSA
R14400
GND
10K
1K
R13248 4
OPT
R14401
R13250
10K U_SPI_WP_f_SoC
U_SPI_WP_f_SoC
10K
OPT
HTPDAn
R13243
10K
Clock for URSA11
LOCKAn
+3.3V_NORMAL
URSA9_CONNECT
LOCKAn_OSD
LOCKAn_Video
R13238
FLASH_WP_URSA
10K
E Q13200
MMBT3906(NXP)
B NXP_LOCKAN_LED_TR
C
Q13200-*1
E
2N3906S-RTK
KEC_LOCKAN_LED_TR
B
C
Chip Config
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V_NORMAL
OPT 10K
10K R13253
R13249
10K
OPT
R13252
10K
R13247
OPT 10K
R13251
10K
R13246
IC13200-*1
W25Q32FVSSIG
WINBOND ELECTRONICS CORP.
URSA11_SERIAL_FLASH_MEMORY_WINBOND(SUB)
EAN62459301
CS VCC
1 8
DO[IO1] HOLD_OR_RESET[IO3]
2 7
WP[IO2] CLK
3 6
IC13200
GND DI[IO0]
4 5
EAN62459501
+3.3V_NORMAL
VCC
C13209
8
0.1uF
16V
HOLD/SIO3
7
10K R13255
SCLK
SPI_CK
6
SI/SIO0
SPI_DI
5
SW13200
1 2
XIN_URSA
3 4
D13200
1N4148W
100V
OPT
XO_URSA
Debugging for URSA11
I2C_S Port
P13200
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
DIM0
1
2
DIM1 R13257 33
3
SCL2_+3.3V_DB
URSA_DEBUG
R13256 33
4
SDA2_+3.3V_DB
URSA_DEBUG
DIM2 5
+3.3V_NORMAL
URSA_PQ_DEBUG
P13201
R13263
12507WS-04L
URSA_PQ_DEBUG
10K
1
33
R13269
2 URSA_UART2_RX
URSA_PQ_DEBUG
3
R13268 33
URSA_UART2_TX
4
URSA_PQ_DEBUG
5 C13212
0.1uF
16V
URSA_PQ_DEBUG
+3.3V_NORMAL
URSA_SYS_DEBUG
P13202
12507WS-04L
R13260
10K
URSA_SYS_DEBUG
1
R13267 33
2 URSA_UART1_RX
URSA_SYS_DEBUG
3
R13266 33
4 URSA_UART1_TX
URSA_SYS_DEBUG
5
C13211
0.1uF
16V
URSA_SYS_DEBUG
URSA Reset
+3.3V_NORMAL
+3.3V_NORMAL
C13210
1uF
R13264
10K
10V
OPT
OPT
URSA_RESET
0
R13259
R13258 URSA_RESET_MICOM
0
470K
OPT R13265
URSA_RESET_SoC
SW13201
JS2235S
1 6
I2C_SCL7 I2C_SDA7
R13261 R13270
0 0
URSA_MP
URSA_MP
2 5
I2CS_SCL
I2CS_SDA
R13262 URSA_DEBUG R13271
0 0
OPT OPT
3 4
SDA2_+3.3V_DB
SCL2_+3.3V_DB
BSD-15Y-LM14A-144_00-HD
URSA11_GPIO
LGE Internal Use Only