Sony STR-DE1075 Service Manual page 51

• DIGITAL BOARD IC1601 CXD9616R (AUDIO DSP2)
Pin No. Pin Name
VDDI
1
EXTIN
2
3, 4 WMD1, WMD0
5 MOD1
MOD0
6
VSS
7
8 XRST
VSS
9
SCKOUT
10
VDDI (PLL)
11
SYNC
12
PAGE2 to PAGE0
13 to 15
16 PLOCK
BTACK
17
VDDE
18
VSS
19
D31 to D29
20 to 22
23 A17
VSS
24
SDO3
25
SDO4
26
27, 28 SDI1, SDI2
LRCKI1
29
VSS
30
D28, D27
31, 32
33 A16
A15
34
SDI3
35
L2
36
37 VDDI
BCKI1
38
SDI4
39
MS
40
41, 42 A14, A13
D26, D25
43, 44
VSS
45
BCKI2
46
47, 48 FS2, FS1
SPDIF
49
A12
50
D24 to D22
51 to 53
54 VDDE
VSS
55
D21 to D19
56 to 58
A11
59
I/O
—
Power supply terminal (+2.5V)
I
Not used (fixed at "L")
I External memory wait mode setting terminal (fixed at "H")
I
Mode select signal input terminal "L": 384fs, "H": 256fs
I
Mode select signal input terminal "L": single chip mode, "H": can not use
—
Ground terminal
I
Reset signal input from the system controller (IC1703)
—
Ground terminal
O
Serial clock signal output to the D/A converter (IC1201, 1202)
—
Power supply terminal (+2.5V) (for PLL)
I
Sync/unsync select signal input terminal "L": sync
O
External memory page select signal output terminal Not used (open)
O
Internal PLL lock signal output teminal Not used (open)
I
Boot mode display signal output teminal Not used (open)
—
Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM (IC1602)
O Address signal output terminal Not used (open)
—
Ground terminal
O
Audio serial data output to the D/A converter (IC1201)
O
Audio serial data output to the D/A converter (IC1202)
I Audio serial data input from the audio DSP1 (IC1501)
I
L/R sampling clock signal input from the audio DSP1 (IC1501)
—
Ground terminal
I/O
Two-way data bus with the S-RAM (IC1602)
O Address signal output terminal Not used (open)
O
Address signal output to the S-RAM (IC1602)
I
Audio serial date input from the audio DSP1 (IC1501)
—
Not used (open)
— Power supply terminal (+2.5V)
I
Bit clock signal input from the audio DSP1 (IC1501)
I
Audio serial data input from the audio DSP1 (IC1501)
I
Master/slave active select terminal "L": internal clock, "H": erternal clock (fixed at "L")
O Address signal output to the S-RAM (IC1602)
I/O
Two-way data bus with the S-RAM (IC1602)
—
Ground terminal
I
Bit clock signal input terminal Not used (open)
I Sampling frequency select signal input terminal Not used (open)
I
S/PDIF output terminal Not used (open)
O
Address signal output to the S-RAM (IC1602)
I/O
Two-way data bus with the S-RAM (IC1602)
— Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM (IC1602)
O
Address signal output to the S-RAM (IC1602)
Description
STR-DE1075
51