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BLOCK DIAGRAM
Figure 2. ST92F124V1: Architectural Block Diagram
AS
DS
RW
WAIT
NMI
DS2
RW
Management
INT[6:0]
WKUP[15:0]
OSCIN
OSCOUT
RESET
CLOCK2/8
INTCLK
CK_AF
STOUT
ICAPA0
OCMPA0
ICAPB0
OCMPB0
EXTCLK0
ICAPA1
OCMPA1
ICAPB1
OCMPB1
EXTCLK1
TINPA0
TOUTA0
TINPB0
TOUTB0
TINPA1
TOUTA1
TINPB1
TOUTB1
V
REG
REGULATOR
The alternate functions (Italic characters) are mapped on Port 0, Port 1, Port2, Port3, Port4, Port5, Port6, Port7,
Port8 and Port9.
FLASH
128 Kbytes
3 TM
E
1 Kbyte
RAM
4 Kbytes
256 bytes
Register File
8/16 bits
CPU
Interrupt
ST9 CORE
RCCU
ST. TIMER
EF TIMER 0
EF TIMER 1
MF TIMER 0
MF TIMER 1
VOLTAGE
Ext. MEM.
ADDRESS
Ext. MEM.
ADDRESS
WATCHDOG
- 45 -
DATA
Port0
Ports
1,9
Fully
Prog.
I/Os
2
I
C BUS
SPI
ADC
SCI M
SCI A
A[7:0]
D[7:0]
A[10:8]
A[21:11]
P0[7:0]
P1[7:3]
P1[2:0]
P2[7:0]
P3[7:4]
P3[3:1]
P4[7:4]
P4[3:0]
P5[7:0]
P6[5:2,0]
P6.1
P7[7:0]
P8[7:0]
P9[7:0]
SDA
SCL
WDOUT
HW0SW1
MISO
MOSI
SCK
SS
AV
DD
AV
SS
AIN[15:8]
AIN[7:0]
EXTRG
TXCLK
RXCLK
SIN
DCD
SOUT
CLKOUT
RTS
RDI
TDO
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