Sony CDX-737 Service Manual page 35

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• MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER)
Pin No. Pin Name
1, 2 NC
3 NC
4 REQ
5 CCLK
6 CSI
7 CSO
8 SCLK
9 SSI
10 NC
ADD0 to ADD7
11 to 18
19 NC
20 to 27 DATA0 to DATA7
28 RST
29 EXTAL
30 XTAL
31 VSS
32 to 55 NC
56 BUSY
57 to 61 NC
TE
L 13942296513
62 CE
63 WE
64 to 69 ADD8 to ADD13
70 VDD
71 NC
72 NC
73 NC
74 ADD14
75 NC
76 SCOR
77 WFCK
78 BUCK
79, 80 NC
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I/O
O Not used (open)
I Not used (fixed at "L")
O
Request signal output to the system controller (IC201) "L" active
I
Serial data transfer clock signal input from the system controller (IC201)
I
Serial data input from the system controller (IC201)
O Serial data output to the system controller (IC201)
O
Clock signal output for subcode data reading to the CXD2530Q (IC101)
I
Subcode data input from the CXD2530Q (IC101)
O Not used (open)
O Address signal output to the S-RAM (IC502)
I Not used (fixed at "L")
I/O
Two-way data bus with the S-RAM (IC502)
System reset signal input from the system controller (IC201), SONY bus interface (IC302) and
I
reset signal generator (IC304) "L": reset
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
I
System clock input terminal (10 MHz)
O
System clock output terminal (10 MHz)
—
Ground terminal
O Not used (open)
O
Busy signal output to the system controller (IC201) "L": busy status
O
Not used (open)
O
Chip enable signal output to the S-RAM (IC502) "L" active
O Data write enable signal output to the S-RAM (IC502) "L" active
O
Address signal output to the S-RAM (IC502)
—
Power supply terminal (+5V)
O
Not used (open)
I Not used (fixed at "L")
I
Not used (fixed at "H")
O
Address signal output to the S-RAM (IC502)
O
Not used (open)
I Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
I
Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101)
I
Backup power supply detection signal input terminal (used also to reset standby)
I
Not used (fixed at "L")
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