TSB41AB1 IEEE 1394a 2000 ONE PORT CABLE TRANSCEIVER/ARBITER SLLS423D – JUNE 2000 – REVISED SEPTEMBER 2002 description (continued) required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it to normal operation.
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TVP5146 1.7 Terminal Functions Table 1–1. Terminal Functions TERMINAL DESCRIPTION NAME NUMBER Analog Video VI_1_A VI_1_x: Analog video input for CVBS/Pb/B/C VI_1_B VI_2_x: Analog video input for CVBS/Y/G VI_1_C VI_3_x: Analog video input for CVBS/Pr/R/C VI_2_A VI_4_A: Analog video input for CVBS/Y VI_2_B Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof) VI_2_C...
TVP5146 Table 1–1. Terminal Functions (Continued) TERMINAL DESCRIPTION NAME NUMBER Host Interface I 2 C clock input I 2 C data bus Power Supplies AGND Analog ground. Connect to analog ground. A18GND_REF Analog 1.8-V return A18VDD_REF Analog power for reference 1.8 V CH1_A18GND CH2_A18GND Analog 1.8-V return...
2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) MM1221~1228 MITSUMI 2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) Monolithic IC MM1221~MM1228 Outline These ICs are high grade video switches with 2-input 1-output or 3-input 1-output and built-in 75Ω driver. The series includes those with and without built-in clamp and 6dB amp circuits.
2-Input 1-Output Video Switch (75Ω driver)/3-Input 1-Output Video Switch (75Ω driver) MM1221~1228 MITSUMI Block Diagram (MM1221~MM1228) Control input truth table Control input truth table Control input truth table Control input truth table...
July 2003 LP2995 DDR Termination Regulator General Description Features n Low output voltage offset The LP2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR- n Works with +5v, +3.3v and 2.5v rails SDRAM.
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TERMINATION TERMINATION AT E5.1 AT DDR The VTT side of the terminaton resistors should be placed on a wide VTT island on the surface layer. The island is located at each end of the bus, so it does not interfere with the signal routing.
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