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Innovative Integration PC44 Hardware Manual

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PC44 Hardware Manual

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  • Page 1 Innovative Integration PC44 Hardware Manual...
  • Page 2 The PC44 Hardware Manual was prepared by the technical staff of Innovative Integration, Aug. ‘95. Third Edition prepared June ‘96 (applies to Rev. E and later cards) For further assistance contact Innovative Integration 31352 W. Via Colinas #101 Westlake Village, California 91362...

  • Page 3: Table Of Contents

    The 82C54 Counter/Timers....................21 1.5.5 Analog I/O ........................... 22 1.5.6 Analog Input........................23 1.5.6.1 PC44 A/D Register Set....................25 1.5.6.2 A/D Conversion Triggering.................... 26 1.5.6.3 A/D Channel Calibration....................27 1.5.6.4 Input Range Control....................... 27 1.5.6.5 Single-Ended/Differential Inputs ................... 28 1.5.6.6 Analog Multiplexer ......................29 1.5.6.7 MUX Software Cautions ....................
  • Page 4 1.5.6.9 Anti-alias Filtering ......................32 1.5.7 Analog Output ........................35 1.5.7.1 D/A Converter Output Ranges..................35 1.5.7.2 D/A Output Trimming ....................36 1.5.7.3 D/A Output Amplification and Filtering ............... 36 1.5.7.4 D/A Converter Control Registers (Software Conversion Triggering)......36 1.5.7.5 D/A Hardware Conversion Triggering................37 1.5.8 Analog Output Bits (ABITS) ....................
  • Page 5 Figure 2: PC44 Communication Port Connections.................. 15 Figure 3: JTAG Connections and Shorting Jumper Functionality ............17 Figure 4: PC44 Multiboard Installation ....................17 Figure 5: Block Diagram of Analog Inputs ....................24 Figure 6: MUX Channel Input Diagram ....................30 Figure 7: Anti-alias Filter Frequency Response..................
  • Page 7 Table 5: Processor C Interrupt Selector ....................14 Table 6: Comm Port Jumper Direction Settings..................16 Table 7: PC44 External Peripheral Memory Map ................. 18 Table 8: Timer Source 0 Selection Jumpers ..................... 20 Table 9: Timer Source 1 Selection Jumpers ..................... 20 Table 10: JP5 Digital I/O Port Direction Jumper Settings..............

  • Page 9: Pc44 Hardware Functions

    1.1 PC44 Bus Interface The PC44 is mapped into the I/O and memory space of the IBM AT. The PC44 supports 16-bit and 32-bit accesses only - no eight bit accesses are supported. The 32-bit operations on the PC bus allow easy use with newer 32-bit protected mode PC software.
  • Page 10 PC44 Hardware Manual - 2 Base + 0xC 16-bit Read/ Write 0x0000 = resource captured 0xFFFF = resource busy Base + 0x10 16-bit Read/ Write 0x0000 = resource captured 0xFFFF = resource busy Base + 0x14 16-bit Read/ Write 0x0000 = resource captured...

  • Page 11: Pc44 Memory

    Innovative Integration. Brands we have tested include Cypress and IDT. The PC44 memory uses a 32-bit wide logical address, the lower 24 bits of which are significant. This is because the 'C44 DSP memory address busses are physically 24 bits wide, but maintain basic compatibility with the original ‘C40 DSP which has 32-bit addressing.

  • Page 12: Local Sram Memory

    SIMMs available as a contiguous memory bank of up to 3M in size. 1.2.4 PC44 Global Memory The PC44 has on-board support for global memory which is arbitrated with a second processor in TIM site A. The global memory, as configured in the GMCR (Global Memory Control Register) by the boot program, is divided into SRAM and expansion EDRAM on global strobe 0 and peripherals on strobe 1.

  • Page 13: Figure 1: Pc44 Memory Map

    PC44 Hardware Manual - 5 Figure 1: PC44 Memory Map Logical Address Physical Address $0000 0000 Boot Loader ROM (internal) $0000 FFFF Reserved $0010 0000 Internal Peripherals $0010 00FF Reserved Reserved Local Space $002F F800 1K RAM Block 0 (internal)

  • Page 14: Wait States

    The startup code routines within the PC44 boot ROM have been customized to automatically perform this initialization during the startup of each application program with zero wait state for on-board local and global SRAM and an appropriate mix of wait states for peripherals.

  • Page 15: Memory Options

    PC44 Hardware Manual - 7 1.2.6 Memory Options The PC44 supports up to 2048 KWords of local SRAM and 1024 KWords of global SRAM on the board without additional hardware. The standard memory configuration shipped is 128 KWords of zero wait state local memory.

  • Page 16: Dual Port Memory

    DIP switch S2 (default D000:0000). Accesses to dual port memory always run with zero wait states from the PC side and two wait states from the PC44 side (after initial global bus arbitration overhead).

  • Page 17: Dual Port Semaphores

    PC44 Hardware Manual - 9 1.2.7.1 Dual Port Semaphores The PC44 dual port has eight semaphores which may be used by software to control the data flow through the dual port memory. The semaphores assist software by providing an arbitration method when accessing the dual port memory.

  • Page 18: Pc44 Boot Prom

    JTAG into SRAM and try again. 3. Use a ROM programmer to burn a new FLASH chip and insert that into the PC44. It is a good idea to read out the existing working monitor program before you reburn the FLASH in case the new program doesn’t work.

  • Page 19: Processor Interrupts

    PC44 Hardware Manual - 11 1.3 Processor Interrupts The PC44 provides the option to generate interrupts to processors attached to the PC44 from a number of on- and off-board sources. These user-selectable connections are made via jumper headers JP41, JP42, and JP43, which each control the interrupts for one processor (there is a maximum of three processors installable on a single PC44).
  • Page 20 2. DPORT_INT: This is an interrupt which can optionally be generated by the dual port memory in both directions, i.e. it can be used by the PC host software to interrupt a processor on the PC44, and can also be used by a PC44 processor to interrupt the PC. The interrupt is triggered and cleared by writing and reading certain dual port memory locations.

  • Page 21: Interrupt Selection

    PC44 Hardware Manual - 13 1.3.3 Interrupt Selection The interrupt headers JP43, JP41, and JP42 select interrupts for processors A, B and C respectively. Table 3: Processor A Interrupt Selector Processor Interrupt Interrupt Source JP43 Jumper Input IIOF0 EXT_INT0 DPORT_INT...

  • Page 22: Table 5: Processor C Interrupt Selector

    PC44 Hardware Manual - 14 Table 5: Processor C Interrupt Selector Processor Interrupt Interrupt Source JP42 Jumper Input IIOF0 EXT_INT0 DPORT_INT TM_SRC0 EXT_TM_SRC0 IIOF1 EXT_INT1 ADC_A_BUSY 9-11 TM_SRC1 8-10 ADC_B_BUSY 10-12 IIOF2 EXT_INT2 13-15 EXT_INT3 15-17 PC_INT2 14-16 EXT_TM_SRC1 16-18...

  • Page 23: Tim40 Expansion Sites

    PC44 Hardware Manual - 15 1.4 TIM40 Expansion Sites The PC44 has two TIM40 sites to allow for additional processors and peripherals. Up to two additional TIM40 standard processors like the Innovative Integration TIM44 or TIM422 may be added to the PC44 to increase processing capability.

  • Page 24: Tim Site Jtag Considerations

    PC44 Hardware Manual - 16 The PC44 also allows the user to force the direction of off-board comm port connections through the use of headers JP51, JP52, JP60, JP61, JP62, and JP63. The position of the shorting jumpers on each header determines the direction (bidirectional, in or out) of the particular comm port (see below for settings).

  • Page 25: Figure 3: Jtag Connections And Shorting Jumper Functionality

    The following diagram shows a typical multiboard installation of the JTAG debugger scan loop. In this case, three PC44’s are installed along with the DEBUG4x scan path controller. Each board has a different number of installed processors to show how the jumpers are setup.

  • Page 26: Peripherals

    Because the offchip peripheral complement on the PC44 has widely varying wait-state requirements, the peripherals in this region have been grouped according to the bus access time of each peripheral. Wait state generation for the peripherals is controlled by a hardware wait state generator included in the PC44 board logic.
  • Page 27 PC44 Hardware Manual - 19 A/D access with post increment ADC_INC_BOTH 0xFFFA 8000 muxes A & B, conversion strobe on both A and B A/D convert start on A ADC_CONV_A 0xFFFA C000 A/D convert start on B ADC_CONV_B 0xFFFB 0000...

  • Page 28: Timer Source Selection

    To help simplify the situation for users, the design of the PC44 employs the concept of timer sources. A timer source is simply a downselection of a few of the possible hardware timer signals down to a single named signal which can more easily be distributed across the PC44.

  • Page 29: Digital Connections

    Lower Half Output Enabled Upper Half Output Enabled The digital I/O port can also be configured to support either a PC44 internally generated readback clock or an externally driven readback clock. This feature allows an external device to synchronously clock data into the PC44’s input buffers.

  • Page 30: Analog I/O

    CLK inputs. When degated, the counters will not tally regardless of their CLK inputs. The gates for each counter are pulled active on the PC44 so that you need not concern yourself with gating the clock to each counter unless it is desirable to do so within your application. If gating is desired within your application, each of the gate signals is accessible on the application connector JP7 and may be driven by TTL signals.

  • Page 31: Analog Input

    Gain and offset errors are trimmable. Standard output voltage range is +/-10V. The PC44 has split internal power and ground planes for maximum performance and noise immunity. Preserving the full 16-bit accuracy depends very much on user cabling and grounding techniques. Use best practices including single point grounds and twisted pair or coax wiring to preserve the 16-bit performance of the PC44.

  • Page 32: Figure 5: Block Diagram Of Analog Inputs

    Control Control The PC44 analog input section is comprised of two channels, each independent, which service up to 8 single-ended inputs or 4 differential inputs each. This results in a total of 16 single-ended or 8 differential inputs. Each channel of the analog input has a separate A/D converter, 6 pole anti-alias filter, programmable gain amplifier, and multiplexer.

  • Page 33: Pc44 A/D Register Set

    1.5.6.1 PC44 A/D Register Set Use of the A/D channels is simplified by the PC44 register set which implements auto-incrementing of the mux inputs and software control of the A/D input range. These registers are implemented in logic on board the PC44 and supplement the actual A/D control registers, detailed below.

  • Page 34: A/D Conversion Triggering

    PC44 Hardware Manual - 26 1.5.6.2 A/D Conversion Triggering A/D conversions may be triggered by any of nine sources, subject to certain combination limitations. The types of conversion triggers are DSP memory-mapped access, timer driven, and external TTL driven. Trigger source selection for either A/D is made using three jumper blocks: JP38, JP39, and JP40. JP38 selects the actual hardware signal used to cause the A/D conversion, while JP39 and JP40 are timer source selectors used to simplify the job of hardware strobe selection (see section 2.3.1 Timer Source Selection for...

  • Page 35: A/D Channel Calibration

    1.5.6.3 A/D Channel Calibration The PC44 A/D inputs are trimmed by a set of potentiometers (R6 and R17 for channel A, R5 and R18 for channel B) on the A/D daughterboard. The A/D offsets and gain are trimmed at the factory prior to shipment, but may require retirmming once user equipment is attached due to external offsets, cable leakage, and other sources of error.

  • Page 36: Single-Ended/Differential Inputs

    PC44 Hardware Manual - 28 1.5.6.5 Single-Ended/Differential Inputs Each of the PC44 ADC input channels is multiplexed via either a four-channel DG409 differential analog mux or an eight-channel DG408 single-ended mux. By using a special socket layout in the board design it is possible to use either a 408 or a 409 for either channel A or B.

  • Page 37: Analog Multiplexer

    PC44 Hardware Manual - 29 1.5.6.6 Analog Multiplexer The multiplexers are four or eight-input channel devices (DG409/408). Each multiplexer has a maximum switching time of 1 us. Channel separation is 68 dB between all channels. Input signals are protected against momentary shorts by the break-before-make switching characteristic of the multiplexer. The multiplexer is best driven from a low impedance output such as an op amp for best performance.

  • Page 38: Figure 6: Mux Channel Input Diagram

    PC44 Hardware Manual - 30 Figure 6: MUX Channel Input Diagram IN10 MUX A (DG408) IN11 Out+ Out- IN10 MUX A (DG409) IN11 IN12 IN13 IN14 MUX B (DG408) IN15 Out+ IN12 Out- IN13 IN14 MUX B (DG409) IN15...

  • Page 39: Mux Software Cautions

    1.5.6.7 MUX Software Cautions When writing software for the PC44 which makes use of the MUXing capabilities of the card, be sure to allow enough time after switching MUX channels for the MUX to settle out. According to the Siliconix data sheets (see Appendix 3.3), the DG409 switches in 180 ns typically.

  • Page 40: Programmable Gain Amplifiers

    Brown programmable gain instrumentation amplifiers may be factory installed as U49 and U50 on the PC44. The PGA205 provides programmable gains of 1, 2, 4 and 8. The PGA204 provides gains of 1, 10, 100, and 1000. It is permissible to employ a PGA204 for one A/D channel and a PGA205 for the other channel.

  • Page 41: Figure 7: Anti-Alias Filter Frequency Response

    PC44 Hardware Manual - 33 Figure 7: Anti-alias Filter Frequency Response 2.7K 3.9K 5.1K 6.8K -100 -120 -140 -160 10000 100000 1000000 Frequency (Hz)

  • Page 42: Figure 8: Anti-Aliasing Filter Schematic

    PC44 Hardware Manual - 34 Figure 8: Anti-aliasing Filter Schematic +5REF 500K C203 C204 1 U51A 33, NON-POLAR U51B 1 U51C AGND AGND -5REF R35A R35B 1 U51D OUT_A R35C R35D R35E R35F IN_A C197 TL074 3.9K 3.9K 220 pF TL074 3.9K...

  • Page 43: Analog Output

    1.5.7 Analog Output Four independent channels of 200 kHz, 16-bit instrumentation-grade digital-to-analog converters (D/A) are provided on the PC44. The D/As are useful for analog signal outputs for both control and signal generation. The D/A converters are double-buffered and the PC44 implements several update methods to accommodate various applications.

  • Page 44: D/A Output Trimming

    1.5.7.2 D/A Output Trimming The PC44 supports an output trim on each D/A output when used in the bipolar mode (no onboard trim is available for the unipolar mode). The trim method outlined below minimizes offset error, gain error, and bipolar zero error.

  • Page 45: D/A Hardware Conversion Triggering

    PC44 Hardware Manual - 37 Table 29: D/A Software Update Registers Address Function 0xFFF8 8000 Load D/A data latches in pair 0,1 0xFFF8 C000 Load D/A data latches in pair 0,1 and update analog outputs 0xFFF9 0000 Load D/A data latches in pair 2,3...

  • Page 46: Analog Output Bits (Abits)

    EXT_TM_SRC1, the sources driving these inputs must be TTL compatible and utilize pulse widths no less than one H1 period in length (50 ns for a 40MHz PC44). The input is sampled and the conversion begins on the rising edge of the input pulse.

  • Page 47: Appendices

    PC44 Hardware Manual - 39 2. Appendices 2.1 Factory Jumper Settings...

  • Page 49: Connector Pinouts

    PC44 Hardware Manual - 40 2.2 Connector Pinouts...

  • Page 50: Figure 9: Jp7 - Digital I/O, External Clocks, And External Interrupts

    PC44 Hardware Manual - 41 Figure 9: JP7 - Digital I/O, External Clocks, and External Interrupts Connector type: .100” square header # of pins: 50, in two rows Mating connector: AMP 746286-9 DX[0..31] DX[0..31] DX10 DX11 11 12 DX12 DX13...

  • Page 51: Figure 10: P1 - External Analog I/O And Power Supplies

    PC44 Hardware Manual - 42 Figure 10: P1 - External Analog I/O and Power Supplies Connector type: DB37, right angle # of pins: 37 Mating connector: AMP 747321-1 ABITS[0..3] ABITS[0..3] ABITS0 ABITS1 ABITS2 ABITS3 DVCC AGND DAC1 DAC1 AGND DAC3...

  • Page 52: Figure 11: Jp31-36 - Processor Communication Port Headers

    PC44 Hardware Manual - 43 Figure 11: JP31-36 - Processor Communication Port Headers Connector type: .100” header # of pins: 26 Mating connector: AMP 746286-6 NEED COMM PORT CONNECTOR HERE JP31: Processor A Com Port 1 JP32: Processor A Com Port 2...

  • Page 54: Component Data Sheets

    PC44 Hardware Manual - 44 2.3 Component Data Sheets...
  • Page 55 82C54 S E M I C O N D U C T O R CMOS Programmable Interval Timer August 1996 Features Description • 8MHz to 12MHz Clock Input Frequency The Harris 82C54 is a high performance CMOS Programma- ble Interval Timer manufactured using an advanced 2 micron •...
  • Page 56 82C54 Ordering Information TEMPERATURE 8MHz 10MHz 12MHz RANGE PACKAGE PKG. NO. CP82C54 CP82C54-10 CP82C54-12 C to +70 24 Lead Plastic DIP E24.6 IP82C54 IP82C54-10 IP82C54-12 C to +85 24 Lead Plastic DIP E24.6 CS82C54 CS82C54-10 CS82C54-12 C to +70 28 Lead PLCC N28.45 IS82C54 IS82C54-10...

  • Page 57: Functional Description

    82C54 Pin Description (Continued) DIP PIN SYMBOL NUMBER TYPE DEFINITION CLK 2 CLOCK 2: Clock input of Counter 2. A0, A1 19 - 20 ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. SELECTS Counter 0 Counter 1...
  • Page 58 82C54 Control Word Register The Control Word Register (Figure 2) is selected by the INTERNAL BUS Read/Write Logic when A1, A0 = 11. If the CPU then does a write operation to the 82C54, the data is stored in the Con- CONTROL STATUS trol Word Register and is interpreted as a Control Word used...
  • Page 59 82C54 Operational Description SC - Select Counter General After power-up, the state of the 82C54 is undefined. The Select Counter 0 Mode, count value, and output of all Counters are undefined. Select Counter 1 How each Counter operates is determined when it is pro- Select Counter 2 grammed.
  • Page 60 82C54 Possible Programming Sequence explained later. The second is a simple read operation of the (Continued) Counter, which is selected with the A1, A0 inputs. The only requirement is that the CLK input of the selected Counter must be inhibited by using either the GATE input or external LSB of Count - Counter 1 logic.
  • Page 61 82C54 1. Read least significant byte. The read-back command may also be used to latch status information of selected counter(s) by setting STATUS bit D4 2. Write new least significant byte. = 0. Status must be latched to be read; status of a counter is 3.
  • Page 62 82C54 Both count and status of the selected counter(s) may be If a new count is written to the Counter it will be loaded on latched simultaneously by setting both COUNT and STATUS the next CLK pulse and counting will continue from the new bits D5, D4 = 0.
  • Page 63 82C54 Mode 1: Hardware Retriggerable One-Shot Mode 2: Rate Generator OUT will be initially high. OUT will go low on the CLK, pulse This Mode functions like a divide-by-N counter. It is typically following a trigger to begin the one-shot pulse, and will remain used to generate a Real Time Clock Interrupt.
  • Page 64 82C54 Mode 3: Square Wave Mode Mode 3 is Implemented as Follows: Mode 3 is typically used for Baud rate generation. Mode 3 is EVEN COUNTS: OUT is initially high. The initial count is similar to Mode 2 except for the duty cycle of OUT. OUT will loaded on one CLK pulse and then is decremented by two initially be high.
  • Page 65 82C54 CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 CW = 1A LSB = 3 GATE GATE CW = 18 LSB = 3 LSB = 2 CW = 1A LSB = 3 LSB = 5 GATE GATE...
  • Page 66 82C54 Counter New counts are loaded and Counters are decremented on MODE MIN COUNT MAX COUNT the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 2 for binary counting and 10 for BCD counting. The counter does not stop when it reaches zero.
  • Page 67 82C54 Absolute Maximum Ratings Thermal Information θ θ Supply Voltage ........+8.0V Thermal Resistance (Typical) C/W) C/W)
  • Page 68 Specifications 82C54 = +5.0V ± 10%, T AC Electrical Specifications C to +70 C (C82C54, C82C54-10, C82C54-12) = -40 C to +85 C (I82C54, I82C54-10, I82C54-12) = -55 C to +125 C (M82C54, M82C54-10, M82C54-12) 82C54 82C54-10 82C54-12 TEST SYMBOL PARAMETER UNITS CONDITIONS...
  • Page 69 82C54 Timing Waveforms A0 - A1 tWA (11) (10) VALID DATA BUS (13) (14) (12) FIGURE 17. WRITE A0 - A1 tAR (1) tRA (3) DATA BUS VALID FIGURE 18. READ (8) (15) RD, WR FIGURE 19. RECOVERY COUNT (SEE NOTE) MODE (23) tWC (28)
  • Page 70 82C54 Burn-In Circuits MD 82C54 CERDIP MR 82C54 CLCC VCC Q2 Q1 OPEN Q3 VCC OPEN VCC/2 OPEN VCC/2 Q6 GND VCC/2 OPEN NOTES: = 5.5V ± 0.5V 8. R4 = 1.8kΩ ±5% 1. V 9. R5 = 1.2kΩ ±5% 2.
  • Page 71 82C54 Die Characteristics DIE DIMENSIONS: BACKSIDE FINISH: Backside Gold 129mils x 155mils x 19mils PASSIVATION: (3270µm x 3940µm x 483µm) Type: Nitrox ± 3.0k Å Å METALLIZATION: Thickness: 10k Type: Si-Al-Cu TRANSISTOR COUNT: 2250 ± 0.75k Å Å Thickness: Metal 1: 8k ±...
  • Page 72 Monolithic 16-Bit DACPORT AD669 FUNCTIONAL BLOCK DIAGRAM FEATURES Complete 16-Bit D/A Function On-Chip Output Amplifier (MSB) (LSB) DB15 High Stability Buried Zener Reference Monolithic BiMOS II Construction 1 LSB Integral Linearity Error 16-BIT LATCH 15-Bit Monotonic over Temperature SPAN/ Microprocessor Compatible BIP OFF 10.05k 16-Bit Parallel Input...
  • Page 73 AD669–SPECIFICATIONS (@ T = +25 C, V = +15 V, V = –15 V, V = +5 V, unless otherwise noted) Model AD669AN/AR AD669AQ/SQ AD669BN/BQ/BR Units RESOLUTION Bits DIGITAL INPUTS (T to T (Logic “1” ) Volts (Logic “0” ) Volts µA = 5.5 V)
  • Page 74 AD669 AC PERFORMANCE CHARACTERISTICS (With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested. ≤ T ≤ T = +15 V, V = –15 V, V = +5 V except where noted.)
  • Page 75 AD669 ESD SENSITIVITY The AD669 features input protection circuitry consisting of large transistors and polysilicon series resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified WARNING! as a Class 2 device.
  • Page 76 AD669 DEFINITIONS OF SPECIFICATIONS THEORY OF OPERATION INTEGRAL NONLINEARITY: Analog Devices defines inte- The AD669 uses an array of bipolar current sources with MOS gral nonlinearity as the maximum deviation of the actual, ad- current steering switches to develop a current proportional to justed DAC output from the ideal analog output (a straight line the applied digital word, ranging from 0 mA to 2 mA.
  • Page 77 AD669 If it is desired to adjust the gain and offset errors to zero, this STEP III . . . BIPOLAR ZERO ADJUST can be accomplished using the circuit shown in Figure 3b. The (Optional) In applications where an accurate zero output is re- adjustment procedure is as follows: quired, set the MSB ON, all other bits OFF, and readjust R2 for zero volts output.
  • Page 78 AD669 allows 5 V, 8.192 V and 10.24 V ranges to be used. For ex- USING THE AD669 WITH THE AD688 HIGH PRECISION ample, by using the AD586 5 V reference, outputs of 0 V to VOLTAGE REFERENCE +5 V unipolar or ± 5 V bipolar can be realized. Using the The AD669 is specified for gain drift from 15 ppm/°C to AD586 voltage reference makes it possible to operate the 25 ppm/°C (depending upon grade) using its internal 10 volt...
  • Page 79 AD669 OUTPUT SETTLING AND GLITCH DIGITAL CIRCUIT DETAILS The AD669’s output buffer amplifier typically settles to within The bus interface logic of the AD669 consists of two indepen- 0.0008% FS (l/2 LSB) of its final value in 8 µs for a full-scale dently addressable registers in two ranks.
  • Page 80 AD669 Unipolar coding is straight binary, where all zeros (0000H) on the data inputs yields a zero analog output and all ones (FFFFH) yields an analog output 1 LSB below full scale. Bipolar coding is offset binary, where an input code of 0000H yields a minus full-scale output, an input of FFFFH yields an ADDRESS BUS output 1 LSB below positive full scale, and zero occurs for an...
  • Page 81 AD669 tied together which configures the input stage as an edge trig- The same procedure is repeated until all three AD669s have had gered 16-bit register. The rising edge of the decoded signal their first rank latches loaded with the desired data. A final write latches the data and updates the output of the DAC.
  • Page 82 AD669 NOISE Analog and digital signals should not share a common path. In high resolution systems, noise is often the limiting factor. A Each signal should have an appropriate analog or digital return 16-bit DAC with a 10 volt span has an LSB size of 153 µV routed close to it.
  • Page 83 AD669 –12– REV. A...
  • Page 84 ADC4320/ADC4322/ ADC4325 Very High Speed 16-Bit, Sampling A/D Converters in a Space-Saving 46-Pin Hybrid Package Introduction The ADC4320, ADC4322, and ADC4325 are complete 16-bit, 1 MHz, 2 MHz, and 500 kHz A/D converter subsystems with a built-in sample-and- hold amplifier in a space-saving 46-pin hybrid package. They offer pin- programmable input voltage ranges of ±2.5V, ±5V, ±10V and 0 to +10V, and have been designed for use in applications, such as ATE, digital os- cilloscopes, medical imaging, radar, sonar, and analytical instrumenta-...
  • Page 85 ADC4320/ADC4322/ ADC4325 Specifications SPECIFICATION ADC4325 ADC4320 ADC4322 ANALOG INPUT Input Voltage Range Bipolar ±2.5V, ±5V, ±10V ±2.5V, ±5V, ±10V ±2.5V, ±5V, ±10V Unipolar 0 to +10V 0 to +10V 0 to +10V Max. Input Without Damage ±15.5V ±15.5V ±15.5V Input Impedance 750 Ω...
  • Page 86 SPECIFICATION (CONT.) ADC4325 ADC4320 ADC4322 Step Response 800 ns Max. to 1 LSB 500 ns Max. to 1 LSB 250 ns Max. to 2 LSBs INTERNAL REFERENCE Voltage +5V, ±0.5% Max. +5V, ±0.5% Max. +5V, ±0.5% Max. Stability 15 ppm/°C Max. 15 ppm/°C Max.
  • Page 87 TYPICAL PERFORMANCE CHARACTERISTICS Fig. 2. ADC4325 Dynamic Characteristics at Fig. 6. ADC4325 Dynamic Characteristics at 100 kHz and 0 dB 195 kHz and –6 dB (±5V Range) Fig. 3. ADC4320 Dynamic Characteristics at Fig. 7. ADC4320 Dynamic Characteristics at 100 kHz and 0 dB 495 kHz and –6 dB Range.
  • Page 88 SPECIFICATIONS PIN # RANGE S/H IN 1 S/H IN2 S/H IN 3 0V to +10V Input Input –5V Ref ±5V Input Input SIG RTN ±2.5V Input Input Input ±10V Input SIG RTN SIG RTN Figure 13. Input Scaling Connections. Continued from page 1. true 16-bit performance, avoiding degradation due to ground loops, signal coupling, jitter and digital noise in- troduced when separate S/H and A/D converters are in-...
  • Page 89 PIN # PIN# Gain Adj. ANA RTN +15V DIG RTN R 1 = 50K +5V REF –15V O/U FLOW R 2 = 50K C 1 = 0.1 µF S/H IN 1 BIT 1N Off Adj. C 2 = 0.1 µF S/H IN 2 BIT 1 Gnd.
  • Page 90 To understand the operating principles of the A/D con- curate and 16-bit linear D/A converter which serves as verters, refer to the timing diagram of Figure 16 and the reference element for the conversion’s second the simplified block diagram of Figure 19. The simpli- pass.
  • Page 91 25 µH TANT TANT 10 µF 16V 10 µF 16V DGND OUFLOW +15V 25 µH TANT TANT D15 (MSB) 6.8 µF 20V 6.8 µF 20V AGND AD Converter TANT TANT –15V 6.8 µF 20V 6.8 µF 20V ANARTN1 +5V2 25 µH +15V1 DIGATN2 –15V1...

  • Page 92: Document Organization

    AMENDMENT Am29F010 Data Sheet 1996 Flash Products Data Book/Handbook INTRODUCTION contained in this document will be included in the next release of the Flash Products Data Book/Handbook. This amendment supersedes information regarding the Am29F010 device in the 1996 Flash Products Data DOCUMENT ORGANIZATION Book/Handbook, PID 11796D.

  • Page 93: Block Diagram

    A M E N D M E N T PRODUCT SELECTOR GUIDE Family Part No: Am29F010 = 5.0 V ± 5% Ordering Part No: V -55 (P) = 5.0 V ± 10% -55 (J,E,F) -120 Max Access Time (ns) CE (E) Access (ns) OE (G) Access (ns) BLOCK DIAGRAM DQ0–DQ7...
  • Page 94 A M E N D M E N T ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM29F010 OPTIONAL PROCESSING Blank = Standard Processing = Burn-In VOLTAGE TOLERANCE ±5%...
  • Page 95 A M E N D M E N T ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature Commercial (C) Devices Plastic Packages ....–65°C to +125°C Ambient Temperature (T ).
  • Page 96 A M E N D M E N T AC CHARACTERISTICS Write/Erase/Program Operations Parameter Symbols JEDEC Standard Description -120 Unit Write Cycle Time (Note 2) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold Time WHDX Read (Note 2) Output Enable...
  • Page 97 A M E N D M E N T AC CHARACTERISTICS Write/Erase/Program Operations Alternate CE Controlled Writes Parameter Symbols JEDEC Standard Description -120 Unit Write Cycle Time (Note 2) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH Data Hold Time EHDX...
  • Page 98 A M E N D M E N T ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Typ (Note 1) Unit Comments Chip/Sector Erase Time 15 (Note 1) Excludes 00H programming prior to erasure µs Byte Programming Time 1000 (Note 3) Excludes system-level overhead (Note 4) Chip Programming Time 12.5 (Notes 3, 5) Excludes system-level overhead (Note 4)
  • Page 99 A M E N D M E N T Am29F010...
  • Page 100 FAST CMOS IDT54/74FCT16952AT/BT/CT/ET IDT54/74FCT162952AT/BT/CT/ET 16-BIT REGISTERED IDT54/74FCT162H952AT/BT/CT/ET TRANSCEIVER Integrated Device Technology, Inc. ET 16-bit registered transceivers are built using advanced FEATURES: dual metal CMOS technology. These high-speed, low-power • Common features: devices are organized as two independent 8-bit D-type regis- –...
  • Page 101 IDT54/74FCT16952AT/BT/CT/ET, 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OEAB OEBA OEAB OEBA CLKAB CLKBA CLKAB CLKBA CEAB CEAB CEBA CEBA SO56-1 E56-1 SO56-2 SO56-3 CEAB CEBA CEAB CEBA CLKAB CLKBA CLKAB CLKBA OEAB OEBA OEAB OEBA...
  • Page 102 IDT54/74FCT16952AT/BT/CT/ET 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES (1,3) FUNCTION TABLE PIN DESCRIPTION Inputs Outputs Pin Names Description CEAB OEAB CEAB OEAB OEAB xCLKAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Clock Enable Input (Active LOW) CEBA...
  • Page 103 IDT54/74FCT16952AT/BT/CT/ET, 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS) Following Conditions Apply Unless Otherwise Specified: = 5.0V ± 10%; Military: T = 5.0V ± 10% Commercial: T = –40°C to +85°C, V = –55°C to +125°C, V Symbol Parameter...
  • Page 104 IDT54/74FCT16952AT/BT/CT/ET 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD) Following Conditions Apply Unless Otherwise Specified: = 5.0V ± 10%; Military: T = 5.0V ± 10% Commercial: T = –40°C to +85°C, V = –55°C to +125°C, V Symbol Parameter...
  • Page 105 IDT54/74FCT16952AT/BT/CT/ET, 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions Min. Typ. Max. Unit ∆I Quiescent Power Supply = Max. — Current TTL Inputs HIGH = 3.4V µA/ Dynamic Power Supply Current = Max., Outputs Open —...
  • Page 106 IDT54/74FCT16952AT/BT/CT/ET 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16952AT/162952AT FCT16952BT/162952BT Com'l. Mil. Com'l. Mil. Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Min. Max. Unit Propagation Delay = 50pF 10.0 11.0 xCLKAB, xCLKBA to xBx, xAx...
  • Page 107 IDT54/74FCT16952AT/BT/CT/ET, 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION Test Switch 7.0V Open Drain 500 Ω Closed Disable Low Enable Low Pulse Open D.U.T. All Other Tests Generator 2515 lnk 12 DEFINITIONS:...
  • Page 108 IDT54/74FCT16952AT/BT/CT/ET 162952AT/BT/CT/ET, 162H952AT/BT/CT/ET FAST CMOS 16-BIT REGISTERED TRANSCEIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION XXXX Device Type Temp. Range Drive Bus Hold Package Process Blank Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 952AT...

  • Page 109: General Description

    19-4334; Rev. 5; 9/95 Low-Cost, µP Supervisory Circuits _______________General Description ___________________________Features The MAX705-MAX708/MAX813L microprocessor (µP) µMAX Package: Smallest 8-Pin SO supervisory circuits reduce the complexity and number Guaranteed RESET Valid at V = 1V of components required to monitor power-supply and Precision Supply-Voltage Monitor battery functions in µP systems.
  • Page 110 Low-Cost, µP Supervisory Circuits ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) SO (derate 5.88mW/°C above +70°C) ....471mW ..........-0.3V to 6.0V µMAX (derate 4.10mW/°C above +70°C) .
  • Page 111 Low-Cost, µP Supervisory Circuits ELECTRICAL CHARACTERISTICS (continued) = 4.75V to 5.5V for MAX705/MAX707/MAX813L, V = 4.5V to 5.5V for MAX706/MAX708, T to T , unless otherwise noted.) PARAMETER SYMBOL CONDITIONS UNITS MR Pull-Up Current MR = 0V µA MR Pulse Width MR Input Threshold High MR to Reset Out Delay (Note 2)
  • Page 112 Low-Cost, µP Supervisory Circuits __________________________________________Typical Operating Characteristics MAX705/MAX707 RESET OUTPUT VOLTAGE MAX705/MAX707 POWER-FAIL COMPARATOR vs. SUPPLY VOLTAGE RESET RESPONSE TIME DE-ASSERTION RESPONSE TIME = +5V = +25°C = +25°C 30pF = +25°C +1.25V +1.30V RESET RESET RESET RESET RESET RESET 330pF 30pF +1.20V...
  • Page 113 Low-Cost, µP Supervisory Circuits ______________________________________________________________Pin Description MAX705/MAX706 MAX707/MAX708 MAX813L NAME FUNCTION DIP/SO µMAX DIP/SO µMAX DIP/SO µMAX Manual-Reset Input triggers a reset pulse when pulled below 0.8V. This active-low input has an inter- nal 250µA pull-up current. It can be driven from a TTL or CMOS logic line as well as shorted to ground with a switch.
  • Page 114 Low-Cost, µP Supervisory Circuits WATCHDOG WATCHDOG TRANSITION TIMER RESET DETECTOR 250µA TIMEBASE FOR RESET AND 250µA WATCHDOG RESET RESET GENERATOR RESET RESET GENERATOR (RESET) MAX707 4.65V* MAX708 MAX705 4.65V* MAX706 MAX813L 1.25V 1.25V * 4.40V FOR MAX7O6. * 4.40V FOR MAX7O6. ( ) ARE FOR MAX813L ONLY.
  • Page 115 Low-Cost, µP Supervisory Circuits Power-Fail Comparator To build an early-warning circuit for power failure, con- nect the PFI pin to a voltage divider (see Typical The power-fail comparator can be used for various pur- Operating Circuit ). Choose the voltage divider ratio so poses because its output and noninverting input are that the voltage at PFI falls below 1.25V just before the not internally connected.
  • Page 116 Low-Cost, µP Supervisory Circuits +12V TO µP RESET MAX70_ MAX70_ 130k RESET PARAMETER UNIT +12V Reset 10.67 10.87 11.50 Threshold at +25°C Figure 5. RESET Valid to Ground Circuit Figure 6. Monitoring Both +5V and +12V BUFFERED RESET TO OTHER SYSTEM COMPONENTS 100k MAX70_ 100k...
  • Page 117 Low-Cost, µP Supervisory Circuits __Ordering Information (continued) _______Pin Configuration (continued) PART TEMP. RANGE PIN-PACKAGE TOP VIEW MAX705EPA -40°C to +85°C 8 Plastic DIP (RESET) RESET MAX705ESA -40°C to +85°C 8 SO MAX705MJA -55°C to +125°C 8 CERDIP** MAX705 MAX706CPA 0°C to +70°C 8 Plastic DIP MAX706 MAX813L...
  • Page 118 Low-Cost, µP Supervisory Circuits _______________________________________________________Package Information INCHES MILLIMETERS 0.036 0.044 0.91 1.11 α 0.004 0.008 0.10 0.20 0.010 0.014 0.25 0.36 0.005 0.007 0.13 0.18 0.101mm 0.116 0.120 2.95 3.05 0.004 in 0.116 0.120 2.95 3.05 0.0256 0.65 0.188 0.198 4.78 5.03 0.016...
  • Page 119 Low-Cost, µP Supervisory Circuits ______________________________________________________________________________________...
  • Page 120 Low-Cost, µP Supervisory Circuits Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 ©...
  • Page 121 ® PGA204 PGA205 Programmable Gain INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION The PGA204 and PGA205 are low cost, general pur- DIGITALLY PROGRAMMABLE GAIN: pose programmable-gain instrumentation amplifiers PGA204: G=1, 10, 100, 1000V/V offering excellent accuracy. Gains are digitally se- PGA205: G=1, 2, 4, 8V/V lected: PGA204—1, 10, 100, 1000, and PGA205—1, µ...

  • Page 122: Specifications

    SPECIFICATIONS ELECTRICAL PGA204 G=1, 10, 100, 1000V/V = ±15V, and R At T = +25°C, V = 2kΩ unless otherwise noted. PGA204BP, BU PGA204AP, AU PARAMETER CONDITIONS UNITS INPUT ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV Offset Voltage, RTI =+25°C ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C...
  • Page 123 SPECIFICATIONS ELECTRICAL PGA205 G=1, 2, 4, 8V/V = ±15V, and R At T = +25°C, V = 2kΩ unless otherwise noted. PGA205BP, BU PGA205AP, AU PARAMETER CONDITIONS UNITS INPUT ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV Offset Voltage, RTI =+25°C ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C...
  • Page 124 PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS Supply Voltage .................. ±18V PACKAGE DRAWING MODEL PACKAGE NUMBER Analog Input Voltage Range ............. ±40V Logic Input Voltage Range ..............±V PGA204AP 16-Pin Plastic DIP Output Short-Circuit (to ground) ..........Continuous PGA204BP 16-Pin Plastic DIP Operating Temperature ..........
  • Page 125 DICE INFORMATION FUNCTION FUNCTION — — – Feedback Dig. Ground V– Substrate Bias: Internally connected to V– power supply. MECHANICAL INFORMATION MILS (0.001") MILLIMETERS 186 x 130 ±5 4.72 x 3.30 ±0.13 Die Size 20 ±3 0.51 ±0.08 Die Thickness Min.
  • Page 126 TYPICAL PERFORMANCE CURVES = ±15V, unless otherwise noted. At T = +25°C, and V GAIN vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY G = 1k,100 G=1k G = 10 G=100 “B” Grade G = 1 G = 1k G=10 G = 100 G = 10 G = 1 100k...
  • Page 127 TYPICAL PERFORMANCE CURVES (CONT) = ±15V, unless otherwise noted. At T = +25°C, and V INPUT-REFERRED INPUT BIAS AND INPUT OFFSET CURRENT OFFSET VOLTAGE WARM-UP vs TIME vs TEMPERATURE > G 100 ±I –2 –1 –4 –6 –2 –75 –50 –25 Time from Power Supply Turn-on (s) Temperature (°C)
  • Page 128 TYPICAL PERFORMANCE CURVES (CONT) = ±15V, unless otherwise noted. At T = +25°C, and V QUIESCENT CURRENT vs TEMPERATURE OUTPUT CURRENT LIMIT vs TEMPERATURE –|I –75 –50 –25 –40 –15 Temperature (°C) Temperature (°C) QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE POSITIVE OUTPUT SWING vs TEMPERATURE = ±15V = 11.4...
  • Page 129 TYPICAL PERFORMANCE CURVES (CONT) = ±15V, unless otherwise noted. At T = +25°C, and V SMALL-SIGNAL RESPONSE, G = 1 LARGE-SIGNAL RESPONSE, G = 1 +200mV +10V –200mV –10V SMALL-SIGNAL RESPONSE, G = 10 LARGE-SIGNAL RESPONSE, G = 10 +200mV +10V –200mV –10V...
  • Page 130 TYPICAL PERFORMANCE CURVES (CONT) = ±15V, unless otherwise noted. At T = +25°C, and V INPUT-REFERRED NOISE, 0.1 TO 10Hz, G = 1000 NOISE, 0.1 TO 10Hz, G = 1 0.2µV/Div 0.5µV/Div 1s/Div 1s/Div APPLICATION INFORMATION be used to sense the output voltage directly at the load for best accuracy.
  • Page 131 Some applications select gain of the PGA204/205 with switches or jumpers. Figure 2 shows pull-up resistors con- Over-Voltage nected to assure a noise-free logic “1” when the switch, Protection – jumper or open-collector logic is open or off. Fixed-gain applications can connect the logic inputs directly to V+ or 100kΩ...
  • Page 132 it to its highest gain and trimming the output voltage to zero with the inputs grounded. Drift performance usually im- proves slightly when the input offset is nulled with this Microphone, procedure. Hydrophone PGA204 etc. Do not use the input offset adjustment to trim system offset or offset produced by a sensor.
  • Page 133 G • V – PGA204 Over-Voltage PGA205 Feedback Protection 25kΩ 25kΩ Digitally Selected Feedback Network Digital Ground Over-Voltage 25kΩ 25kΩ Protection G • V V– FIGURE 5. Voltage Swing of A and A Input-overload often produces an output voltage that appears normal.
  • Page 134 +15V HI-509 PGA204 Over-Voltage PGA205 Feedback Protection – 25kΩ 25kΩ Digitally Selected Feedback Network Over-Voltage 25kΩ 25kΩ Protection 3 15 V– –15V Data Out To Address 74HC574 Decoding Logic Data In Data Bus FIGURE 7. Multiplexed-Input Programmable Gain IA. – PGA204 PGA205 20kΩ...
  • Page 135 Index BIP/UP*, 34 bipolar/unipolar input range (A/D's), 33 block transfers, 17 boot code, 11 boot FLASH reprogramming, 18 32-bit addressing, 11 boot loader, 18 boot ROM, 14, 18 boot.asm, 14 bypassing the MUX's, 39 82C54, 20, 27, 28, 30, 57 82C54 clock sources, 30 82C54 timer gating, 30 CACK, 59...
  • Page 136 DPORT_INT, 20 INPUT_B, 39, 58 DPORT_SEM, 26 Installation, 1, 7 dual port, 1, 4, 5, 8, 9, 16, 17, 20 INT_A_TO_B, 20, 26 Dual Port RAM, 4 INT_B_TO_A, 20, 26 Dual Port Semaphores, 9 interlock, 12 interprocessor interrupts, 20 dual/quad configurations, 48 DUAL_PORT, 26 interprocessor messaging, 20 interrupt conflicts, 19...
  • Page 137 PC Int1, 9 strobe, 11, 12, 13, 14, 27, 28, 29, 36, 48, 57, 59 PC_INT0, 20 PC_INT1, 20 PC44 Bus Interface, 9 peripheral, 2, 3, 4, 8, 12, 15, 26, 34, 47, 49 peripheral wait state generation, 26 TCLK, 28...

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