Yaesu FT-227RB Instruction Manual page 16

Scanning memorizer 2 meter fm transceiver
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SQ IN
0
1
0713 0714
DC AMP
0702 1/6
DELAY
0701 1/2
0701 1/2
D.
F/F(CK)
0707 2/6
1 STEP GATE
0704 i/4
...I
0707 1/6
DELAY
0704 2/4
UPO-ci- a ad 0707 2/6
D N
SCHMITT
...L:
02 1/6
DELAY
D.F/F (U/D)
M. PLEXER
M. VIBRATOR
0
0703 1/6
0709-0711
U/DCCUNTER
CK 0
u/DO
INV
0703 1/6
Q704 1/4
ER
0708 2/4
B W CONT
INV
M PLEX
0702. 703. 707. HEX INVERTER
0704. QUAD 21NPUT NAND GATE
0708. QUAD 2INPUT AND GATE
0703 1/6
DE
LAY
ir! ' ,11-0-•
BCD
1
0705.0706
RAM
M. CH
Q712
BCD-DECIMAL
DECODER
0715
RELAY DR I V
0702
TX CONT
The digital phase comparator,
Q309
(TC5081P),
compares the phase of the PLL IF signal with that
of the reference signal, and any difference is con-
verted into an error-correcting voltage. This error-
correcting voltage is fed to varactor diode
D301 ,
which changes the output signal phase to lock with
that of the reference signal.
PLL CONTROL UNIT
Please refer to the PLL Control Unit logic diagram
for questions regarding the operation of this cir-
cuitry. A complete treatment of every logic state
is beyond the scope of this manual.
When the VCO is locked, the constant voltage at
pin 4 of
Q309
is applied to
Q316
(MPSA13), caus-
ing it to conduct; in turn,
Q315
(2SC372Y) cuts
off. The H voltage at the collector of
Q315
causes
Q205
(2SC372Y) to conduct, supplying DC voltage
to exciter stages
Q204
and
Q206 .
When the VCO is
unlocked, the DC voltage at the emitter of
Q205
drops, preventing normal operation of
Q204
and
Q206 •
The output voltage from
Q31. 5
is reversed in
polarity by Q314 (2SC372Y), and applied to
Q606
(2SC372Y), keeping the collector of
Q606
at the
H level, in order to drive
Q601 - Q603
(MSM561)
for the display of the channel frequency. The volt-
age is also applied to
Q105
(2SA564), which
supplies DC voltage to the second heterodyne
oscillator,
Q104
(2SC372Y).
When the VCO is unlocked, the collector of DC
voltage drops, causing the LEDs to turn off.
Simultaneously, the second heterodyne oscillator
ceases to oscillate. The receiver is thus muted until
VCO lock occurs.
Crystal
Frequency
PLL Het. Freq.
Remarks
X301
44.10000 MHz
132.300 MHz
Simplex
X302
43.90000
/'
131.700
//
TX —600 kHz shift
X303
44.30000
-
132.900
/-
TX +600 kHz shift
X304
44.10166
••
132.305
,
Simplex 5 kHz up
X305
43.90166
',
131.705
,
TX —600 kHz 5 kHz up
X306
44.30166
,
132.905
,
TX +600 kHz 5 kHz up

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