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CIRCUIT DIAGRAM 4
1
3530
1K
4511
I2C_DATA
7509
A
BC847BW
+3V3_DAC
B
+5V
+3V3_DPL
INTREQ
C
dpl_d
D
E
1
11-10
2
3
3531
1K
4512
I2C_DPL_DATA
I2C_DPL_CLK
I2C_CLK4
7507
BC847BW
+3V3_DAC
5502
+3V3_DPL
100u
3,4V
7508
CS492705-CL
3515 4K7
VA
VD
Φ
37
DD
3514
4K7
38
DC
AUDIO
20
INTREQ
DECODER
3511
10K
ABOOT
18
+3V3_DPL
CS
7
I2C_DPL_CLK
SCCLK
MCLK
3512
10K
6
SCDIN
+3V3_DPL
A 0:1
LRCLK
3516
4K7
36
RESET
17
+5V
0
AUDAT
EM0
16
EM1
1
15
EM2
2
SDATAN1
14
3
SDATAN2
EM3
11
DATA
EM4
4
CMPDAT
10
EM5
5
CMPCLK
9
dpl_d
EM6
6
SCLKN2
8
EM7
7
CMPREQ
EMAD 0:7
LRCLKN2
GPIO 0:7
SCLKN1
21
O_P
EXTMEM
STCCLK2
GPIO8
LRCLKN1
19
I2C_DPL_DATA
SCDIO
SCDOUT
XMT958
MUX
PSEL
GPIO9
CLKIN
4
10K
WR
+3V3_DPL
DS
CLKSEL
3521
EMWR
GPIO10
C_E
5
RD
R|W_
EMOE
GPIO11
DGND
AGND
dpl_d
2
3
4
5
MUX
1
15
dpl_d
2
DPL_LS_RS
3
PCM_LS_RS
5
DPL_C_LFE
6
PCM_C_LFE
11
10
dpl_d
14
+3.3VA
13
dpl_d
2512
100n
dpl_d
DPL_MCLK
44
3513
43
DPL_BCLK
SCLK
42
DPL_WCLK
47R
41
DPL_L_R
0
40
1
DPL_LS_RS
39
2
DPL_C_LFE
22
AUX_DATA
27
DPL_IN_DATA
28
DPL_MCLK
DPL_IN_BCLK
29
DPL_IN_WCLK
25
DPL_BCLK
DPL_WCLK
26
DPL_WCLK
PCM_WCLK
3
DPL_BCLK
3517
30
DPLII_CLKIN
PCM_BCLK
33R
31
DPL_L_R
2514
33
FILT1
PCM_L_R
220n
32
FILT2
dpl_d
2523
dpl_d
220n
+3.3VA
4
5
11-10
6
7
+3V3_DAC
7505
3,3V
74LVC157A
100n
2507
16
G1
VCC
8
EN
GND
dpl_d
MUX_PCM_LS_RS
1~
MUX
4
1
MUX_PCM_C_LFE
7
9
12
4506
4505
+3V3_DAC
7506
3,3V
74LVC157A
2508
1
16
G1
VCC
MUX
100n
15
8
EN
GND
dpl_d
dpl_d
2
1~
MUX
4
MUX_MCLK
3
MCLK
1
5
MUX_WCLK
7
6
11
MUX_BCLK
9
10
14
MUX_PCM_L_R
12
13
4503
4504
3139 113 3503 pt4 sheet 4 dd wk321
6
7
2507 A7
2508 C7
2509 B3
2510 B3
2511 B4
2512 B4
2513 E4
2514 E5
2515 D3
2520 E5
2521 E5
A
2523 E5
3509 C4
3510 C2
3511 C3
3512 C3
3513 C5
3514 C3
3515 C3
3516 C2
3517 D4
3518 E5
3519 A2
3520 A3
3521 E3
B
3522 C2
3530 A2
3531 A3
4503 E7
4504 E7
4505 C7
4506 C7
4507 B5
4508 B5
4511 A2
4512 A3
C
5502 B4
7505 A6
7506 C6
7507 A3
7508 C3
7509 A1
D
E
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