Sony STR-DA2ES Service Manual page 66

STR-DA2ES/DB1080
Pin No.
Pin Name
46 LRCK EN
47 ERROR
48 NC
49 SUB.T.PORT
50 SP B
51 GND
52 MD2
53, 54 MD1, MD0
55 RSTX
56 VCC
57 X1
58 X0
59 VSS
60 STOP
61 RDS CLK
62 POWER
63 MBUS TV
64 MBUS DVD
65 MBUS VIDEO
66 SIRCS
67 DIR ERROR
68 VCC
69 XSTATE
70 DATA0
71 XMODE
72 CKSEL1
73 CLK
74 CE
75
DI
76 DO
77 VCC
78 BST2
79 PM2
80 XRST2
81 HACN2
82 HCS2
83 GB9
84 BST1
85 HCS1
86 A1 IN
87 A1 OUT
88 HACN1
89 XRST1
66
I/O
O Signal selection signal output "L": boot strap signal, "H": L/R sampling clock signal
I
Error signal input from the audio digital signal processor 2
I
Not used
O
Sub power on/off signal output "H": power on
Front B speaker on/off switch input terminal "L": speaker on
I
(except STR-DB1080: E model)
— Ground terminal
O
Setting terminal for the CPU operation mode Fixed at "L" in this set
O
Setting terminal for the CPU operation mode Fixed at "H" in this set
System reset signal input "L": reset
I
For several hundreds msec. after the power supply rises, "L" is input, then it changes to "H"
— Power supply terminal (+3.3V)
O
Main system clock output terminal (16.5 MHz)
I
Main system clock input terminal (16.5 MHz)
—
Ground terminal
I Sub power voltage detection signal input
RDS serial data transfer clock signal input from the tuner unit
I
(STR-DB1080: AEP and UK models only)
I
I/1 key input terminal
I
TV and SAT signal input terminal (STR-DA2ES only)
I
DVD and LD signal input terminal (STR-DA2ES only)
I VIDEO signal input terminal (STR-DA2ES only)
I
Sircs signal input
I
PLL lock error signal and data error flag input from the digital audio interface receiver
—
Power supply terminal (+3.3V)
I Source clock selection monitor input from the digital audio interface receiver
I
Audio serial data input from the digital audio interface receiver
O
System reset signal output to the digital audio interface receiver "L": reset
O
Output clock selection signal output to the digital audio interface receiver
O Clock signal output to the digital audio interface receiver
O
Chip enable signal output to the digital audio interface receiver
O
Write data output to the digital audio interface receiver
I
Read data input from the digital audio interface receiver
— Power supply terminal (+3.3V)
O
Boot strap control signal output to the audio digital signal processor 2
O
PLL initialize signal output to the audio digital signal processor 2
O
System reset signal output to the audio digital signal processor 2 "L": reset
I Acknowledge signal input from the audio digital signal processor 2
O
Chip select signal output to the audio digital signal processor 2
I
Audio signal input from the audio digital signal processor 1
O
Boot strap signal output to the audio digital signal processor 1
O Chip select signal output to the audio digital signal processor 1
I
Sircs signal input for CONTROL A1 II
O
Sircs signal output for CONTROL A1 II
I
Acknowledge signal input from the audio digital signal processor 1
O System reset signal output to the audio digital signal processor 1 "L": reset
Description