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FastVision FastCamera13 User Manual

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FASTCAMERA SERIES
FASTCAMERA13
USER'S MANUAL
FVM-50013

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Summary of Contents for FastVision FastCamera13

  • Page 1 FASTCAMERA SERIES FASTCAMERA13 USER’S MANUAL FVM-50013...
  • Page 2 FastVision, LLC. FastVision makes no warranty for the use of its products, assumes no responsibility for any error, which may appear in this document, and makes no commitment to update the information contained herein.

  • Page 3: Table Of Contents

    TABLE OF CONTENTS INTRODUCTION _________________________________________________ 1-6 Features and Specifications _______________________________________ 2-6 2.1. CAMERA SPECIFICATIONS ____________________________________________ 2-7 2.2. IMAGE SENSOR SPECIFICATIONS: ______________________________________ 2-7 2.3. Physical Specifications ________________________________________________ 2-7 2.4. Connectors __________________________________________________________ 2-9 2.4.1. Power Connector HR10A-10R-12PB__________________________________________ 2-9 2.4.2. Data Connector J2________________________________________________________ 2-9 2.4.3.
  • Page 4 The hardware connections are:______________________________________ 23-45 23.3. The software connections are: ______________________________________ 23-46 23.4. Using a FastVision supplied framegrabber ____________________________ 23-46 23.4.1. The hardware connections are: ____________________________________________ 23-47 23.4.2. The software connections are:_____________________________________________ 23-47 23.5. Using a third-party framegrabber ____________________________________ 23-48 23.5.1.
  • Page 5 TROUBLESHOOTING __________________________________________ 24-50 FastVision TECHNICAL SUPPORT________________________________ 25-50 25.1. Contacting Technical Support_______________________________________ 25-50 25.2. Returning Products for Repair or Replacements _______________________ 25-50 25.3. Reporting Bugs ___________________________________________________ 25-51...

  • Page 6: Introduction

    1. INTRODUCTION The FastCamera13 is a 1.3 megapixel CMOS camera with internal memory and FPGA’s that enable it to do real-time processing. Thus it is what one would term a “smart” camera. The standard programming that is supplied with the base camera forms the basis of the most used and demanded function for data processing.

  • Page 7: Camera Specifications

    2.1. CAMERA SPECIFICATIONS • The FastCamera13 uses a 1280H x 1024V (1.3 megapixel) CMOS digital image sensor capable of 500 frames/second operation at full resolution • 1280H x 1024V image resolution • 12-micron-square active-pixel photodiodes • 500+ frames per second, progressive-scan •...
  • Page 8 FASTCAMERA13 CASE AND MOUNTING DIMENSIONS FastCam era13 Front View FastCam era13 FastCam era13 Back Panel Side View 74.0m m 12.7mm 39.5m 0 ref 0 ref 7m m FastCam era13 Bottom View...

  • Page 9: Connectors

    2.4. Connectors 2.4.1. Power Connector HR10A-10R-12PB Function Ground +5 Volts Ground Reserved for application dependent I/O Ground +5 Volts Reserved for application dependent I/O Ground +5 Volts Reserved for application dependent I/O +5 Volts Reserved for application dependent I/O 2.4.2. Data Connector J2 Signal Signal Ground...

  • Page 10: Power Requirements

    3. POWER REQUIREMENTS Power requirements are a strong function of the specific application; the camera is 15 Watts worst case, 5 to 10 Watts typical. Low noise +5 Volt input recommended. Internally the camera has high frequency switching supplies that convert the 5 volt input to 3.3, 2.5 and 1.8 volts. 4.
  • Page 11 CL1_C[7:0] pixels 4*n+2 CL2_A[7:0] pixels 4*n+3 CL1_B[1:0],CL1_A[7:0] 4*n+0 Four Taps 10 bits CL1_B[5:4],CL1_C[7:0] 4*n+1 (Medium) CL2_C[1:0],CL2_B[7:0] 4*n+2 CL2_C[4:5],CL2_A[7:0] 4*n+3 CL1_A[7:0] pixels 5*n+0 Five Taps 8 bits CL1_B[7:0] pixels 5*n+1 (Medium) CL1_C[7:0] pixels 5*n+2 CL2_A[7:0] pixels 5*n+3 CL2_B[7:0] pixels 5*n+4 CL1_B[1:0],CL1_A[7:0] 5*n+0 Five Taps 10 bits CL1_B[5:4],CL1_C[7:0] 5*n+1 (Full)

  • Page 12: Camera Data Flow

    Other modes are possible with custom FPGA configurations purchased from FastVision or developed in- house. 6. CAMERA DATA FLOW Tables By Pixel Data Camera Sensor Gain & Format Links Offset Funnel Serial 128-1000M B SRAM Serial Settings Exposure Settings Memory...

  • Page 13: The Standard Camera Functionality

    The ‘Standard’ Camera is a set of FPGAs designed to support most of the typical uses of the camera. It is a good starting point for modifications. This design is copyrighted IP from FastVision and forms the reference design, which is available from FastVision for use only with the FastCamera13.

  • Page 14: Circular Buffer Memory Mode

    9.2. Circular buffer memory mode In this mode the memory is used as a circular buffer. Each time an image is presented to the memory it is stored over-writing the oldest image in the buffer. When CC2 goes active (or via a serial command), the filling operation stops, after a selected number of frames are added to the memory buffer (delayed trigger).

  • Page 15: Line Timing

    13.1. Line Timing Sensor line and frame rates are controlled by the Camera State settings. The minimum line period depends on the sensor type and the ROI width. When the Line Period setting exceeds the minimum period, extra clocks are inserted between lines. The Line Valid period only depends on the ROI width and sensor type.

  • Page 16: Trigger Options

    There are four basic trigger modes: • Free-running mode ignores trigger inputs and reads out the sensor continuously at a programmed frame rate with programmed exposure timing. • Multi-frame edge-triggered mode activates a programmed number of exposures after a programmed delay at a programmed frame rate with programmed exposure timing.

  • Page 17: Trigger Outputs

    There are four trigger sources - Camera Link CC1, TTL trigger input, Serial, and USB (via I2C). • The CC1 and TTL sources can be enabled or disabled. They can also be active high (positive-going edge for edge-triggering or high level for external exposure) or active low (negative-going edge for edge-triggering or low level for external exposure).

  • Page 18: Flash Memory

    The Control FPGA has a small embedded micro that runs through an initialization sequence at power-on. This same micro also implements the host, USB, and Data FPGA communication protocols and deals with flash memory and DAC’s. 1. Immediately after power-on, the voltage reference DAC’s are programmed with factory default values. This allows the sensor to stabilize under conditions close to the actual operating environment.

  • Page 19: Camera State Storage

    Table 2 - Flash Memory Layout Table 3 shows the layout of the first page in flash memory. This contains enough descriptors for the Camera Control GUI to determine the camera type and its options. This data should only be programmed by Fast-Vision.

  • Page 20: Serial Control Interface

    2 ROI Start Line 2 ROI End Line 2 Line Period in Pixel Clocks 4 Exposure Time in Pixel Clocks 4 Frame Period in Pixel Clocks 4 Exposure Delay in Pixel Clocks 2 Serial Link Bit Period in Pixel Clocks 1 Camera Link Readout Mode 1 Camera Link Clock Frequency 1 Binning...

  • Page 21: Encoding

    16.1. Encoding Commands and response use the 7-bit ASCII code zero-extended to 8 bits. This is sometimes refered to as 8 bits, no parity or 7-bits space parity. For characters that require escape codes as listed below, the 8 bit is significant in the decoding, so only the normal character encoding needs to be escaped. For example hex 0d requires the escape sequence but hex 8d does not.
  • Page 22 All commands end in a non-escaped carriage-return, hex 0d. When commands take arguments in hex, data must consist of pairs of hex characters representing full bytes. Within each byte the most significant nibble is sent first, but for multi-byte values the least significant byte is normally sent first.
  • Page 23 This command takes no arguments. The camera responds with “H” followed by eight hex digits and a carriage-return. The eight hex digits indicate the value of a free-running 32-bit frame counter. This counter indicates all frames read from the sensor since power on, not necessarily the number of frames sent to the framegrabber.
  • Page 24 0x85 Main memory page program through buffer 2 The following non-write commands are also implemented with Write Flash: 0x53 Main memory Page to Buffer 1 Transfer 0x55 Main memory Page to Buffer 2 Transfer 0x60 Main memory Page to Buffer 1 Compare 0x61 Main memory Page to Buffer 2 Compare 0x58...

  • Page 25: Inter-Fpga Communication

    This is the only Control FPGA response that uses binary encoded arguments (with escape codes for <cr> and \). The camera responds with “M” followed by escaped binary data from the flash and finally a non-escaped carriage-return. Internally the Control FPGA waits for the flash to become non-busy then starts the flash read operation.

  • Page 26: Embedded Soft Processor Core

    Serial Commands Commands from the host are buffered and passed to the Data FPGA on the FPGA_CTL3 wire. The Data FPGA therefore receives all commands from the host and can act on them accordingly. This allows extensions to be made to the command set for Data FPGA use. To reduce logic in the Data FPGA, each character is buffered and retransmitted at 66 MHz, synchronous to the FPGA_SYSCLK.
  • Page 27 The PicoBlaze data address space is only 256 bytes. If you look at the processor documents from Xilinx you’ll find this called I/O rather than data. In our case the data space connects to 1K bytes of internal block RAM using three additional banking bits implemented as register. Access to the entire 1K of RAM as well as 8 registers is accomplished with some stunt logic.
  • Page 28 Serial trigger. Must be toggled in software to trigger the sensor control logic in response to a serial trigger command. Reserved. Calibrate sensor. This is a pulsed signal that schedules a calibration when this bit is written to 1. Writing this bit to zero has no effect. Actual calibration may happen much later, since the sensor control logic schedules calibration only between frames.
  • Page 29 0xFF FPGA Configuration. Bit 6 is reserved. Other bits are: Read only “Fget8” status. This is high when the sequencer is still running from a prior operation. FPGA Loaded on write, FPGA Done on read. Writing this bit high indicates that the program has finished loading the data FPGA and enables the pinsaver muxes.
  • Page 30 0x2C Line Period, low 8 bits. 0x2D Line Period, high 8 bits. This is the line readout time in pixel clocks - 1. i.e. the actual period is one clock more than this number. 0x2E Exposure Period, bits <7:0> 0x2F Exposure Period, bits <15:8>...

  • Page 31: Data Fpga

    Enable Camera Link CC2. Set this bit to 1 to enable CC2 Readout Image. When enabled, the active edge of CC2 causes the current memory image to be read out. DATA FPGA This specification contains an overview of the functionality and design details for the Data FPGA within the FastCamera 13/40.

  • Page 33: Video Data Path Overview

    19.2. Video Data path overview The DataFpga accepts video data from the sensor and formats it for transmission over the Camera Link outputs or USB interface. The ControlFPGA controls the sensor data output and sends Lval (line valid) and Fval (frame valid) signals to the DataFPGA. The data from the sensor is valid when Lval and Fval are asserted.

  • Page 34: Datafpga State Controls

    Vbias1: 30 00 Vref3: 32 E8 Vbias2: 40 00 Vref4: 41 36 Vbias3: 50 00 Vln1: 54 D9 Vbias4: 60 00 Vlp: 64 D9 Vunused1: 70 00 Vclamp3: 70 00 Vunused2: 80 00 Vrstpix: 8D 17 ROI Start Pixel ROI End Pixel ROI Start Line ROI End Line Line Period in Pixel Clocks...
  • Page 35 0x00 CL1_A[7:0] Single tap 8 bits (Basic) 0x01 CL1_B[1:0],CL1_A[7:0] Single tap 10 bits (Basic) (default mode) 0x02 CL1_B[3:0],CL1_A[7:0] Single tap 12-bits (Basic) 0x03 CL1_B[7:0],CL1_A[7:0] Single tap 16-bits (Basic) 0x04 CL1_A[7:0] even pixels (0,2,...) Two Taps 8 bits (Basic) CL1_B[7:0] odd pixels (1,3,...) 0x05 CL1_B[1:0],CL1_A[7:0] even Two Taps 10 bits (Basic)
  • Page 36 Tx10 Tx10 Tx10 Tx11 Tx11 Tx11 Tx12 Tx12 Tx12 Tx13 Tx13 Tx13 Tx14 Tx14 Tx14 Tx15 Tx15 Tx15 Tx16 Tx16 Tx16 Tx17 Tx17 Tx17 Tx18 Tx18 Tx18 Tx19 Tx19 Tx19 Tx20 Tx20 Tx20 Tx21 Tx21 Tx21 Tx22 Tx22 Tx22 Tx23 Tx23 Tx23 LVAL...

  • Page 37: Binning Control Setting

    Tx14 Tx14 Tx14 Tx15 Tx15 Tx15 Tx16 Tx16 Tx16 Tx17 Tx17 Tx17 Tx18 Tx18 Tx18 Tx19 Tx19 Tx19 Tx20 Tx20 Tx20 Tx21 Tx21 Tx21 Tx22 Tx22 Tx22 Tx23 Tx23 Tx23 LVAL Tx24 Tx24 Tx24 FVAL Tx25 Tx25 Tx25 Tx26 Tx26 Tx26 Tx27 LVAL...

  • Page 38: Frame Rates

    FRAME RATES. The actual Frame rate of the camera is determined by settings within the ControlFPGA and the DateFPGA. The ControlFPGA settings determine the data rate from the sensor by adjusting the ROI (Region of Interest), exposure rate and exposure delay. The DataFPGA settings determine the binning settings(which can increase frame rate as there is less data to send over the Camera Link Interface), the Camera link mode and clock speed.
  • Page 39 The following diagrams show simplified state diagrams used to design the Camera Link output stage of the DataFPGA. The data from the FIFOs are fed to 5-to-1 muxes on order to limit the fanout of the data from the FIFO. There are 8 muxs in order to support 8 Tap mode.

  • Page 40: Tap Mode

    The following notes apply for these timing diagrams • CLK0 is the camera link output clock • Empty is the signal from the FIFO that starts the state machine operation in these simplified state diagrams. The actual verilog code used a combination of Empty and other conditions to insure that the FIFO did not under-run.

  • Page 41: Tap Mode

    20.4. 2 Tap mode When the FIFO deasserts empty the state machine starts with a pre-read of the whole FIFO during which pixels 1-Ten are read. The state machine then continues in a 5 cycle loop until the end of the line is detected (ff_lval deasserted).

  • Page 42: Tap Mode

    20.5. 4 Tap mode When the FIFO deasserts empty the state machine starts with a pre-read of the whole FIFO during which pixels 1-Ten are read. The state machine then continues in a 5 cycle loop until the end of the line is detected (ff_lval deasserted).

  • Page 43: Tap Mode

    20.6. 8 Tap mode When the FIFO deasserts empty the state machine starts with a pre-read of the whole FIFO during which pixels 1-Ten are read. The state machine then continues in a 5 cycle loop until the end of the line is detected (ff_lval deasserted).

  • Page 44: Sensor Interface

    20.7. Sensor Interface The FPGA interface to the sensor consists of the following signals: • mv_hsck4,2,1,0 • mv_hsck0, • mv_hsck1, • mv_hsck2, • mv_hsck4, • mv_sel0, • mv_sel1, • mv_sel2, • mv_sel4, • mv_hsd, • mv_data...

  • Page 45: Usb Camera Option

    FastVision supplied USB software for your OS. All of the above can be supplied to you by FastVision. The software (item #4) provides two forms of access to the camera, via a library (DLL, or ActiveX control under Windows, linkable library under other operating systems), and via the supplied application called FastViewer.

  • Page 46: The Software Connections Are

    Operating FastVision System Provided Device Provided Device Camera Drivers Driver Library, FastVision FastViewer ActiveX Software Control 23.4. Using a FastVision supplied framegrabber In this mode of operation you will need the following items, which can all be supplied by FastVision.

  • Page 47: The Hardware Connections Are

    The Camera and a lens A power supply for the camera One or more Camera Link cables FastVision supplied framegrabber FastVision supplied framegrabber software. 23.4.1. The hardware connections are: Power Supply Your Computer FastVision Camera Provided Frame Grabber 1 or 2...

  • Page 48: Using A Third-Party Framegrabber

    The Camera and a lens A power supply for the camera. One or more Camera Link cables. Your third-party framegrabber. AIA compliant software for your framegrabber. FastVision supplied camera control program. 23.5.1. The hardware connections are: Power Supply Your Computer...

  • Page 49: The Software Connections Are

    Grabber Devices Camera Link Standard DLL FastVision Camera Control Application This will only work if your framegrabber supports the Camera Link standard serial interface protocol, and your framegrabber vendor has provided the needed DLL. Otherwise you will have to send commands to the...

  • Page 50: Troubleshooting

    The release notes are available in the directory: \usr\fastvision\alinfo FASTVISION TECHNICAL SUPPORT FastVision offers technical support to any licensed user during the normal business hours of 9 a.m. to 5 p.m. EST. We offer assistance on all aspects of camera installation and operation.

  • Page 51: Reporting Bugs

    If you do not have Internet access, or if it is inconvenient for you to get to access, copy the code to a disk, describe the error, and mail the disk to Technical Support at the FastVision address below. If the code is small enough, you can also FAX the code module to us as indicated below.
  • Page 52 Remember to include the name and telephone number of the person we should contact if we have questions. FastVision, LLC. 131 Daniel Webster Highway #529 Nashua, NH 03060 Telephone: 603-891-4317 FAX: 603-891-1881 Web site: http://www.fast-vision.com/ Electronic Mail: sales@fast-vision.com support@fast-vision.com...

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