LG GD510 Service Manual page 18

GD510 Operational Description
ARM-Memory
- 32k Byte Boot ROM on the AHB
- 96k Byte SRAM on the AHB, flexibly usable as program or data RAM
- 16k Byte Cache for Program (internal)
- 8k Byte tightly coupled memory for Program(internal)
- 8k Byte Cache for Data(internal)
- 8k Byte tightly coupled memory for Data(internal)
DSP-Memory
- 104K x 16bit Program ROM
- 8k x 16bit Program RAM
- 60k x 16bit Data ROM
- 37k x 16bit Data RAM
- Incremental Redundancy(IR) Memory of 35904 words of 16bit
Shared Memory Block
1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.
Controller Bus system
The processor cores and their peripherals are connected by powerful buses.
Multi-layer AHB for connecting the ARM and the other master capable building blocks with the internal
and external memories and with the peripheral buses.
Clock system
The clock system allows widely independent selection of frequencies for the essential parts of the
S-GOLD3. Thus power consumption and performance can be optimized for each application.
Functional Hardware block
- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
- GMSK Modulator: gauss-filter with B*T=0.3
- EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
- Hardware accelerators for equalizer and channel decoding.
- Incremental Redundancy memory for EDGE class 12 support
- A5/1, A5/2, A5/3 Cipher unit
- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
- Advanced static and dynamic power management features including TDMA-Frame
synchronous low power mode and enhanced CPU modes(idle and sleep modes)
- Pulse Number Modulation output for Automatic Frequency Correction(AFC)
- Serial RF Control interface: support of direct conversion RF
- A Universal Serial Interface(USIF) enabling asynchronous (UART) of synchronous (SPI)
serial data transmission
- 3 USIF with autobaud detection, hardware flow control and integrated
- A dedicated Fas IfDA Controller supporting IrDA's SIR,MIR and FIR standards
(up to 4Mbps)
- I2C-bus interface (e.g. connection to S/M power)
- A fast display interface supporting serial and parallel interconnection
- An ITU-R BT.656 compatible Camera interface.
- Programmable clock output for a camera
- An multimedia/Secure Digital Card Interface (MMCI/SD:SDIO capable)
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3. Technical brief
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