Summary of Contents for Elan Microelectronics EM60000 series
- Page 1 EM60000 Series 8-Bit Micro-Controller Based Sound Processor USER’S MANUAL Doc. Version 2.0 ELAN MICROELECTRONICS CORP. March 2003...
- Page 2 Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this publication. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising out of the use of such information or material.
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Page 3: Table Of Contents
Data Move Instruction: ..............9 2.2.2 ALU Related Status Flags................9 2.3 Hardware Multiplier....................10 2.4 Memory Organization....................11 2.4.1 Data Memory ....................11 2.4.2 Program Memory ..................13 2.4.3 Address Mode ....................14 2.4.4 Voice ROM ....................15 Contents • iii EM60000 Series User’s Manual... -
Page 4: System Control
3.8.1 TCC Timer .......................28 3.8.2 MTC Timer ......................28 3.8.3 Speech Timer ....................29 3.8.4 Watchdog Timers .....................29 3.9 I/O Port Control ......................30 3.9.1 Port 1........................31 3.9.2 Port 2........................31 3.9.3 Port 3........................32 3.9.4 Port 4........................33 3.9.5 Port 5........................34 iv • Contents EM60000 Series User’s Manual... - Page 5 5.3.5 CALL – Subroutine Call ................52 5.3.6 CLR – Clear Register..................53 5.3.7 COM – Complement R .................53 5.3.8 COMA – Complement R and Place in Acc...........53 5.3.9 DAA – Decimal Adjust .................54 5.3.10 DEC – Decrement R ..................54 Contents • v EM60000 Series User’s Manual...
- Page 6 5.3.38 SUB – Subtract ....................68 5.3.39 SWAP – Swap High/Low Nibble..............69 5.3.40 SWAPA – Swap High/Low Nibble and Place in Acc........70 5.3.41 WDTC – Clear Watchdog Timer ..............70 5.3.42 XOR – Exclusive OR...................70 vi • Contents EM60000 Series User’s Manual...
- Page 7 6.9.1 Example - Playing Melody ................96 6.10 Power Down Mode ....................99 6.10.1 Example - Power Down and Wake Up by Input Port .........100 6.10.2 Example - Power Down Mode Application for Keyboard-Scan ....100 Contents • vii EM60000 Series User’s Manual...
- Page 8 Contents viii • Contents EM60000 Series User’s Manual...
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Page 9: Introduction
Chapter 1 Introduction 1.1 General Description EM60000 series is an 8-bit micro-controller based sound processor IC featuring audio function that delivers multi-channel instrument playback. The micro-controller consists of – a powerful 8-bit RISC CPU that handles most of the speech/melody... -
Page 10: Block Diagram
8-bit D/A I/O Control Port 1 Port 2 Port 3 Port 4 Port 5 1.4 Parts List The EM60000 series IC’s are equipped with 8K×13 bit program ROM and 144 bytes RAM. Part Output Speech Melody Voice ROM Input Pin... -
Page 11: Pin Assignments
Reset pin (active low, internal pull-high) 1.6 Specifications 1.6.1 Absolute Maximum Ratings Parameter Specification Supply Voltage (V -0.3V to +6.0V Input Voltage -0.3V to V +0.3V Operating Temperature 0°C to 50°C Storage Temperature -55°C to 125°C Introduction • 3 EM60000 Series User’s Manual... -
Page 12: Electrical Characteristics (Temperature: 0°C To 50°C, Vss=0V)
Frequency Range =2.4V 1.6.3 Internal Oscillator Frequency External Resistor (R System Frequency (F 200 K ohms 1MHz 100 K ohms 2MHz 50 K ohms 4MHz 25 K ohms 6MHz 12.5 K ohms 8MHz 4 • Introduction EM60000 Series User’s Manual... -
Page 13: Architecture
ALU also supports BCD decimal arithmetic operations. Data Memory The data memory of EM60000 series has a total of 144 bytes with direct and indirect address modes. Three locations of the data memory are set aside to be shared by the multiplier. All operations can be applied directly to the data memory. -
Page 14: Functional Block Diagram
Chapter 2 Program Counter and Hardware Stack The program counter of EM60000 series is 13 bits in length and provides 8K program ROM address. The program counter is mapped to the data memory and operates by direct instruction. Note that such operations take two instructions cycles to perform. -
Page 15: Hardware Summary
I/O function control (input/output, pull-low, wake-up, etc) 2.2 Arithmetic Logic Unit (ALU) The EM60000 series contain an 8-bit accumulator and an 8-bit arithmetic logic unit that can perform 2’s-complement arithmetic operation, Boolean operation, rotation, bit manipulation, data move, etc. There are several flags in the status register to indicate the result of the operations. -
Page 16: Alu Instruction Summary
Decrease memory content by 1. If the result is zero, skip the next instruction. Decrease memory content by 1 and load result into ACC. If DJZA the result is zero, skip the next instruction. 8 • Architecture EM60000 Series User’s Manual... -
Page 17: Bit Manipulated Instruction
Carry flag. C=1 if there is carry-out after an ALU operation Auxiliary carry flag. DC=1 if a carry comes from the low nibble to the high nibble of the ALU Zero flag. Z=1 if the operation is zero Architecture • 9 EM60000 Series User’s Manual... -
Page 18: Hardware Multiplier
Chapter 2 2.3 Hardware Multiplier The EM60000 series incorporate an 8 x 8 hardware multiplier. By making multiplications a hardware function, the operation can be completed in a single instruction cycle. The operation is a signed multiplication and provides a signed 16-bit result. -
Page 19: Memory Organization
2.4.1 Data Memory All the 144 bytes data memory of EM60000 series can be made the operand of an instruction. The data memory address range is from 0x00 to 0x3F. The lower address locations (0x00 to 0x1F) are reserved for the system control registers, I/O port data registers, and some other general-purpose data memory. - Page 20 2. Refer to Chapter 3; Section 3.3 for detailed discussion of the I/O mapped control registers. 3. All the data memory will NOT initialize after a reset. 4. Grayed blocks are the control register banks for Special Function Control. 12 • Architecture EM60000 Series User’s Manual...
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Page 21: Program Memory
Chapter 2 2.4.2 Program Memory The EM60000 series have a 13-bit program counter that is capable of addressing an 8K x 13 program memory space. The reset vector is at 0x000 and the interrupt vectors are at 0x0002, 0x000A, and 0x000E. The remaining space is for your program use. -
Page 22: Address Mode
When a program writes the address value N in R4, all the instructions that access R0 will operate on the location N of the data memory. The following example will further illustrates the Indirect Address operation: 14 • Architecture EM60000 Series User’s Manual... -
Page 23: Voice Rom
0x00 to 0x3F. 2.4.4 Voice ROM The EM60000 series provide a large voice ROM for speech/instrument playback and user’s applications. The voice ROM can be accessed through hardware or software. Generally, you need to first write the address of the desired data and then read the data through a special I/O mapped control register. - Page 24 Chapter 2 16 • Architecture EM60000 Series User’s Manual...
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Page 25: System Control
Chapter 3 System Control 3.1 Intoduction The system control in the EM60000 series is supported by the program counter, hardware stack, interrupts, reset, sleep/wake-up hardware, timers, and I/O control. A set of system control registers is responsible for all these mechanisms. -
Page 26: R3 (Status Flag Register)
Chapter 3 3.2.1 R3 (Status Flag Register) The Status Flag Register contains important status information; including the status of the ALU, processor-reset condition, and program page select bits. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Description... -
Page 27: R5 (Interrupt Control Register)
2. The reset initial value of Bits 0 ~ 3 is “0.” The reset initial value of Bit 7 is “1”. 3. Bits 4 ~ 6 are not used. Writing data into these bits is invalid and the read value from these bits is unknown. System Control • 19 EM60000 Series User’s Manual... -
Page 28: R8 (Port & Wdt Control Register)
Chapter 3 3.2.4 R8 (Port & WDT Control Register) The R8 Register contains I/O port pull-low control bits, wake-up function control bits, and the watchdog timer enable bit. Use the pull-low control bits to enable/disable the pull-low function of Port 1 and Port 2. Use the wake-up control bit to enable/disable the Port 2 wake-up function. -
Page 29: R9 (Bank Select For Special Function)
Chapter 3 3.2.5 R9 (Bank Select for Special Function) The EM60000 series have a powerful audio processing ability, such as speech/voice processing, instrument melody playback, flexible D/A converter mixing functions, etc. These special functions have their own control registers mapped in one data memory location (RA, address: 0x0A) and several I/O mapped control registers (IOC6~IOCC). -
Page 30: I/O Mapped Control Registers
Chapter 3 3.3 I/O Mapped Control Registers In addition to data memory mapped system control registers, some control registers are I/O mapped and have different access method. The following table will show the functions and locations of these registers. I/O Address Function Prescaler control register 0x6 ~ 0xC... - Page 31 Bit 5 ~ Bit 7 (MSR0 ~ MSR2): MCC prescaler bit. The base frequency is Fosc/2 and the initial value is (1,1,1). MSR2 MSR1 MSR0 MTC Rate 1:16 1:32 1:64 1:128 1:256 System Control • 23 EM60000 Series User’s Manual...
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Page 32: Program Counter And Stack
Chapter 3 3.4 Program Counter and Stack The EM60000 series contain a 13-bit Program Counter (PC) and a hardware stack of 8 levels in depth. See Section 2.4.2 Program Memory of this manual for more detailed description. The Program Counter is memory-mapped to R2 in data memory, so you can use instructions to access the Program Counter. -
Page 33: Tcc Timer Interrupt
Hence you can only access RAM Bank 3 even if you have changed to other bank. R9 is also fixed to Speech Channels 1 or 2 even if you have changed the R9 value. System Control • 25 EM60000 Series User’s Manual... -
Page 34: Reset
Chapter 3 3.6 Reset A RESET can be initiated by one of the following: A power-on reset. The RESET pin is at a low condition (level hold). The Watchdog timer has timed out (if the Watchdog timer is enabled). Some control registers are not affected by a reset condition. Their status is unknown during a power-on reset. -
Page 35: Sleep Mode And Wake Up
3.8 Timer Control A set of timers is available from the EM60000 series ready for your audio processing and other applications. Of these, two are general purpose timers (TCC & MTC), two Speech Timers, and one Watchdog Timer. By taking advantage of the timer’s full set functions, sophisticated multi-channel... -
Page 36: Tcc Timer
Chapter 3 3.8.1 TCC Timer The TCC Timer is a general-purpose timer with an "up" counter equipped with a prescaler. The base frequency is half of the system clock (Fosc/2), which is divided by the prescaler. The divided clock signal is then sent to the TCC counter. -
Page 37: Speech Timer
A prescaler is also provided to generate different clock rates for the WDT clock source. The WS0 & WS1 bits of the IOC5 register define the pre-scale ratio ranging from 1:1 to 1:8. System Control • 29 EM60000 Series User’s Manual... -
Page 38: I/O Port Control
Chapter 3 3.9 I/O Port Control The EM60000 series provide up to five I/O ports, designated as Port 1 through Port 5. Port 1 is a fixed input port, Port 2 ~ 4 are bi-directional I/O ports, and Port 5 is a fixed output port. The I/O port data registers are data memory that are mapped and accessed just like any other data memory. -
Page 39: Port 1
Bit value=1: the relative pin is in “HIGH” status. Each bit value reflects the status of its corresponding I/O pin. Because Port 2 is a bi-directional port, the RC register can be read or written. System Control • 31 EM60000 Series User’s Manual... -
Page 40: Port 3
Chapter 3 IOCD Bit Field: IOCD Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port 2 Pin P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Bit value=0: the relative pin is configured as Output pin. Bit value=1: the relative pin is configured as Input pin. -
Page 41: Port 4
Bit value=1: the relative pin is configured as input pin. Port 4 will be configured as an input port during a reset condition and the initial value of IOCF is all “1.” System Control • 33 EM60000 Series User’s Manual... -
Page 42: Port 5
Chapter 3 3.9.5 Port 5 Port 5 is a common output port. The pin data is latched in RF (data memory address: 0x0F). You can read the pin status data or write the output data through a memory access instruction. RF Bit Field: RF Bit Bit 7... -
Page 43: Special Function Control
Special Function Control 4.1 Introduction The EM60000 series provide powerful functions for multi-channel speech voice processing, high quality instrument melody playback, and D/A mixing. A large voice ROM is available for voice synthesis and general-purpose data storage. These powerful functions require the support of a set of control registers. -
Page 44: Speech Function Control
Chapter 4 Bank assignment for special function control: R9 Value Functions Control Register Locations 0x00 Speech Channel 1 RA, IOC6 ~ IOCC 0x01 Speech Channel 2 RA, IOC6 ~ IOCC 0x02 Voice ROM access IOC6 ~ IOC9 0x04 Melody Channel 1 RA, IOC6 ~ IOCC 0x05 Melody Channel 2... -
Page 45: Ra (Mode Register)
1. The reset initial values of Bits 0 and 1, are “0”. 2. Bits 2~7 are unused, writing data into these bits is invalid and the value read from these bits is unknown. Special Function Control • 37 EM60000 Series User’s Manual... -
Page 46: Ioc6, 7, 8 (Address Registers)
Chapter 4 4.2.2 IOC6, 7, 8 (Address Registers) Speech Channel 1 16 15 IOC8 (ADDH) IOC7 (ADDM) IOC6 (ADDL) Each speech channel has its own address pointer for speech data access. The addresses are written by user and stored in IOC6 ~ IOC8 and is a 20 bits in total length. -
Page 47: Ioca (Sampling Rate Register)
For example, if the system clock Fosc = 4MHz, and the speech sampling rate is 8KHz, the reload value will be 4000000/8/8000 = 62.5, so the you can use 62 as the reload value. The reset initial value is zero. Special Function Control • 39 EM60000 Series User’s Manual... -
Page 48: Iocb, Iocc (Dac Output Registers)
Chapter 4 4.2.5 IOCB, IOCC (DAC Output Registers) In speech function control, IOCB, and IOCC act as output windows to the mixers of DAC 1 and 2. While speech synthesizing, the program will write the synthesis data to IOCB or IOCC, and the data are fed to the mixers of DAC 1 or DAC 2 at the next speech timer underflow. -
Page 49: Ra (Mode Register)
The maximum address capacity is 256K bytes, which means the instrument waveforms should be stored in the first 256K bytes in the voice ROM. These registers cannot be read by the your program. Special Function Control • 41 EM60000 Series User’s Manual... -
Page 50: Ioca (Envelope Register)
Chapter 4 4.3.3 IOCA (Envelope Register) The envelope register stores the envelope value for the current melody channel. Your program should calculate the proper envelope value to obtain a suitable ADSR (Attack-Decay-Sustain-Release) for different instruments. The tone generator will automatically process the waveform data with the envelope and then synthesize the final instrument melody to the mixers of the D/A converters. -
Page 51: Ioc6, 7, 8 (Address Registers)
Output of Speech Channel 2 Output of melody Channel 1 Selector Mixer Output of melody Channel 2 Output of melody Channel 3 Output of melody Channel 4 data) (8-bit signed IOC6 DAC_ON SETR0~ Special Function Control • 43 EM60000 Series User’s Manual... -
Page 52: Ra (Mode Registers)
Chapter 4 4.5.1 RA (MODE Registers) The RA register is used to control the DAC volume, to set the dynamic range of the mixer, and to turn the mixer and DAC on/off. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1... -
Page 53: Ioc6 (Selector Registers)
MCH3=1: Output of melody Channel 3 will be sent to the mixer MCH4=0: Output of melody Channel 4 will not be sent to the mixer Bit 5 (MCH4) MCH4=1: Output of melody Channel 4 will be sent to the mixer Special Function Control • 45 EM60000 Series User’s Manual... - Page 54 Chapter 4 46 • Special Function Control EM60000Series User’s Manual...
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Page 55: Instruction Set
0x80 or 80h 0xFF or 0FFh In hexadecimal representation, if the leading character is not a digit, a “0” prefix must be added. For example, use “0FFh” or “0xFF” instead of “FFh”. Instruction Set • 47 EM60000 Series User’s Manual... -
Page 56: Instruction Summary
Chapter 5 5.2 Instruction Summary Each instruction cycle takes two system clocks, namely, Fosc/2. All of the instructions are single instruction cycle except for the following: Skip operation: JBS, JBC, JZ, JZA, DJZ, DJZA, etc. When a skip occurs, it will take 2 instruction cycles. - Page 57 1dkk SUB A,@k Z,C,DC (k-A→A) Multiply R10 by immediate value k 1 1110 kkkk kkkk 1ekk MPY @k (R10×k→R12:R11) 1 1111 kkkk kkkk 1fkk ADD A,@k Z,C,DC Add immediate value k to Acc (A+k→A) Instruction Set • 49 EM60000 Series User’s Manual...
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Page 58: Instruction Description
Chapter 5 5.3 Instruction Description 5.3.1 ADD – Addition ADD A, R Syntax Encoding 0011 10rr rrrr A+R→A Operation Status Affected Z, C, DC Add the contents of data memory R to the accumulator. Place the result in Description the accumulator. ADD A, 0x10 ;... -
Page 59: And - And Operation
AND the contents of the accumulator with the immediate data (8-bit Description literal) Place the result in the accumulator. AND A, @0xFF Example ; Acc = Acc & 0xFF AND A, @0xAA ; Acc = Acc & 0xAA Instruction Set • 51 EM60000 Series User’s Manual... -
Page 60: Bc - Bit Clear
Chapter 5 5.3.3 BC – Bit Clear BC R, b Syntax Encoding 100b bbrr rrrr 0→R(b) Operation None Status Affected Description Bit “b” in the data memory or register R is cleared. 0x03, 0 ; clear carry flag in Status register Example 0x0C, 7 ;... -
Page 61: Clr - Clear Register
A, @0x55 ; R10 = 0x55 Example 0x10, A COMA 0x10 ; Acc = 0xAA, R10 unchanged COMA 0x0C ; Acc = toggle of port 2, port 2 unchanged Instruction Set • 53 EM60000 Series User’s Manual... -
Page 62: Daa - Decimal Adjust
Chapter 5 5.3.9 DAA – Decimal Adjust Syntax Encoding 0000 0000 0001 If [A(3:0) > 9].OR.[DC=1] Operation Then A(3:0) + 6 → A(3:0); If [A(7:4) > 9].OR.[C=1] Then A(7:4) + 6 → A(7:4); Status Affected DAA adjusts the 8-bit value in the accumulator, which is the sum of an Description earlier addition of two variables (each in packed-BCD format), and produces two 4-bit digits. -
Page 63: Deca - Decrement R And Place In Acc
Example MOV A, @0x10 ; R10 = 0x10 MOV 0x10, A LOOP: … DJZ 0x10 ; R10 = R10 – 1 JMP LOOP ; if result! = 0, go to LOOP … Instruction Set • 55 EM60000 Series User’s Manual... -
Page 64: Djza - Decrement R And Place In Acc (Skip If Result Is Zero)
Chapter 5 5.3.13 DJZA – Decrement R and Place in Acc (Skip if Result is Zero) DJZA R Syntax 0101 10rr rrrr Encoding Operation R-1→A, skip next instruction if the result is zero. Status Affected None Decrease the contentsof data memory R by 1. The result is placed in the Description accumulator. -
Page 65: Inc - Increment R
None Move data from the I/O mapped control register IOCR to the Description accumulator. Obtain contents of IOCF, then store into R10. Example ; read IOCF 0x10, A ; store in R10 Instruction Set • 57 EM60000 Series User’s Manual... -
Page 66: Iow - Move Acc To Iocr
Chapter 5 5.3.18 IOW – Move Acc to IOCR IOW R Syntax Encoding 0000 0000 rrrr A→IOCR Operation None Status Affected Description Move data from the accumulator to I/O mapped control register IOCR. Example Set the even bits of Port 2 as output pins. The direction control register of Port 2 is IOCD (0x0D). -
Page 67: Jmp - Unconditional Branch
The following codes illustrate how to make a 256-iteration loop MOV A, @0 ; R10 = 0 MOV 0x10, A LOOP: … 0x10 ; R10 = R10 + 1 JMP LOOP ; if result!=0, go to LOOP … Instruction Set • 59 EM60000 Series User’s Manual... -
Page 68: Jza - Increment R And Place In Acc (Skip If Result Is Zero)
Chapter 5 5.3.23 JZA – Increment R and Place in Acc (Skip if result is zero) JZA R Syntax Encoding 0111 11rr rrrr R+1→A, skip next instruction if result is zero Operation None Status Affected Increase the contents of data memory R. The result is placed in the Description accumulator. -
Page 69: Mpy - Multiply
R12:R11. The operation is signed-multiply. MOV A, @10 ; R10 = 10 Example MOV 0x10, A MOV A, @20 ; R13 = 20 MOV 0x13, A MPY 0x13 ; R12:R11 = R10 * R13 Instruction Set • 61 EM60000 Series User’s Manual... -
Page 70: Nop - No Operation
Chapter 5 Syntax MPY @k 1110 kkkk kkkk Encoding Operation R10×k→R12:R11 None Status Affected Multiply R10 with immediate data k (8-bit literal). The 16-bit result is Description stored in the R12:R11. The operation is signed-multiply. MOV A, @10 Example ; R10 = 10 MOV 0x10, A MPY @20 ;... -
Page 71: Page - Set Page Bits
Move immediate data n (3-bit literal) into page select bit (PS2 ~ PS0 in Description status register (R3). Example PAGE 1 ; set page bits = 1 LABEL ; jump to “LABEL” in Page 1 … ORG 0x0400 LABEL: … Instruction Set • 63 EM60000 Series User’s Manual... -
Page 72: Ret - Return From Subroutine
Chapter 5 5.3.29 RET – Return from Subroutine Syntax Encoding 0000 0001 0010 [Top of stack] →PC Operation None Status Affected Return from subroutine. Stack is popped and the top of the stack is Description loaded into the PC. TEST: A, @0 Example …... -
Page 73: Retl - Return Immediate Data To The A Register
; output to 7-segment LED … TABLE: ADD 0x02, A ; add PC with Acc RETL @0b11111100 RETL @0b01100000 RETL @0b01100000 RETL @0b11110010 RETL @0b01100110 RETL @0b10110110 RETL @0b10111110 RETL @0b11100000 RETL @0b11111110 RETL @0b11110110 Instruction Set • 65 EM60000 Series User’s Manual... -
Page 74: Rets - Return From Speech Subroutine
Chapter 5 5.3.32 RETS – Return from Speech Subroutine RETS Syntax 0000 0001 0100 Encoding [Top of stack] →PC, enable global interrupt flag, restore Acc, status Operation register, and multiplier registers. Status Affected None Return from speech interrupt subroutine. Stack is popped and the top of Description the stack is loaded into the PC. -
Page 75: Rlca - Rotate Left Through Carry And Place In Acc
Set carry to 0 first, and then rotate R10 right by 1-bit. Example MOV A, @0xAA ; R10 = 0xAA MOV 0x10, A 0x03, 0 ; clear carry bit RRC 0x10 ; R10 = 0x55 Instruction Set • 67 EM60000 Series User’s Manual... -
Page 76: Rrca - Rotate Right Through Carry And Place In Acc
Chapter 5 5.3.36 RRCA – Rotate Right through Carry and Place in Acc RRCA R Syntax Encoding 0110 00rr rrrr R (n)→A (n-1), carry→A (7), R (0)→carry Operation Status Affected The contents of data memory R are rotated 1-bit to the right through the Description carry flag. -
Page 77: Swap - Swap High/Low Nibble
R (3:0) ↔ R (7:4) Operation Status Affected None Swap the upper and lower nibbles of data memory R. Description A, @0xF0 ; R10 = 0xF0 Example 0x10, A SWAP 0x10 ; R10 = 0x0F Instruction Set • 69 EM60000 Series User’s Manual... -
Page 78: Swapa - Swap High/Low Nibble And Place In Acc
Chapter 5 5.3.40 SWAPA – Swap High/Low Nibble and Place in Acc SWAPA R Syntax Encoding 0111 00rr rrrr R (3:0) →A (7:4), R (7:4) →A (3:0) Operation None Status Affected The upper and lower nibbles of data memory R are switched over. The Description result is placed in the accumulator. - Page 79 Exclusive OR the contents of the accumulator with the immediate data k Description (8-bit literal). The result is placed in the accumulator. MOV A, @0x55 ; Acc = 0x55 Example XOR A, @0xAA ; Acc = Acc ^ 0xAA = 0xFF Instruction Set • 71 EM60000 Series User’s Manual...
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Page 81: Software Application
Chapter 6 Chapter 6 Software Application 6.1 Introduction The EM60000 series provide flexible control and instrument playback ability utilizing an advanced architecture and powerful instruction set. This chapter, discusses the software application for EM60000 series including the following topics: Program initialization... -
Page 82: Example - Power-On Initialization
Chapter 6 Speech Channels 1 & 2: RA (MODE): Bits 0 & 1 are set to “0.” IOCA & IOCB (D/A outputs) are set to “0.” IOCC (Sampling rate) is set to “0.” Melody Channels 1 & 4: RA (MODE): Bit 0 is set to “0.” IOCA (Envelope) is set to “0.”... - Page 83 ; set Port 4 as output MOV A, @0 ; clear RAM: R10 to R1F of Bank 0 MOV 0x4, A CLEAR_RAM: CLR 0x0 INC 0x4 MOV A, 0x4 XOR A, @0x20 JBS 0x3, 2 JMP CLEAR_RAM Software Application • 75 EM60000 Series User’s Manual...
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Page 84: Program Control
Chapter 6 6.3 Program Control The EM60000 series provide easy but powerful program control instructions, such as: jump, call, computed jump, test/skip, etc. The following examples demonstrate some of the simple program controls. 6.3.1 Example 1 - Using DJZ or DJZA ;--------------------------------------------------------------... -
Page 85: Logic And Arithmetic Operation
Chapter 6 6.4 Logic and Arithmetic Operation The EM60000 series provide a complete set of logic and arithmetic operations, as shown in section on Arithmetic Logic Unit (Section 2.2 of Chapter 2). The operations include AND, COM, COMA, OR, XOR, CLR, RLC, RLCA, RRC, RRCA, BC, BS, ADD, DAA, DEC, DECA, INC, MPY, SUB, and INCA. -
Page 86: Example - Applying The Or Instruction
Chapter 6 6.4.2 Example - Applying the OR Instruction. ;-------------------------------------------------------------- ; The routine demonstrates the OR instruction. ;-------------------------------------------------------------- ORG 0x0000 JMP POWERON ; go to power-on procedure ORG 0x0010 ; power-on reset procedure POWERON: MOV A, @0b00111100 MOV 0x15, A ;... -
Page 87: Example - Applying The Add, Inc, And Inca Instructions
;-------------------------------------------------------------- DEC 0x16 ; R16=3 DEC 0x16 ; R16=2 DECA 0x16 ; A=1 SUB 0x15, A ; R15=R15-A=0x14 ;-------------------------------------------------------------- MOV A, @0x02 ; A=2 SUB A, @0x15 ; A=0x15-A=0x13 OVER: JMP OVER Software Application • 79 EM60000 Series User’s Manual... -
Page 88: I/O Port Applications
Chapter 6 6.5 I/O Port Applications The EM60000 series provide one 8-bit input port (Port 1) and one 8-bit I/O port (Port 2) with pull-low/wake-up function. furthermore, it also provides two additional general-purpose I/O ports (Port3 and 4), and one output port (Port5). - Page 89 ; debounce time 20 ms JBS 0x0B,3 ; detect p1.3?=1: Y->p3.3=1 JMP POLLING N->keep polling TR4: MOV A, @0b00001000 MOV 0x0D, A ; p3.3 set to high JMP POLLING ; go back for polling Software Application • 81 EM60000 Series User’s Manual...
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Page 90: Example - Simple Keyboard Scan (16 Keys)
Chapter 6 ;-------------------------------------------------------------- ; delay subroutine for Fosc = 4MHz ; total delay=(1+1+200+200+200*100+200*100+200+200)*0.5us=20.4ms ;-------------------------------------------------------------- DELAY20: MOV A, @200 ; 1 cycle MOV 0x14, A ; 1 cycle DL20: MOV A, @100 ; 200 cycles MOV 0x15, A ; 200 cycles DL21: DJZ 0x15 ;... - Page 91 ; debounce time 20 ms JBS 0x0B, 0 ; check p1.0?=1 JMP PORT2SCAN ; p1.0=0 -> port2_scan CALL CHECK1 JBC 0x03, 2 ; check zero flag R3(2)?=0 JMP TR1 ; R3(2)=1 -> tr1 CALL CHECK5 Software Application • 83 EM60000 Series User’s Manual...
- Page 92 Chapter 6 JBC 0x03, 2 ; check zero flag R3(2)?=0 JMP TR5 ; R3(2)=1 -> tr5 CALL CHECK9 JBC 0x03, 2 ; check zero flag R3(2)?=0 JMP TR9 ; R3(2)=1 -> tr9 CALL CHECK13 JBC 0x03, 2 ; check zero flag R3(2)?=0 JMP TR13 ;...
- Page 93 JMP PORT2SCAN TR7: MOV A, @0x07 ; tr7-> write “7” to port 3 MOV 0x0D,A JMP PORT2SCAN TR8: MOV A, @0x08 ; tr8-> write “8” to port 3 MOV 0x0D, A JMP PORT2SCAN Software Application • 85 EM60000 Series User’s Manual...
- Page 94 Chapter 6 TR9: MOV A, @0x09 ; tr9-> write “9” to port 3 MOV 0x0D, A JMP PORT2SCAN TR10: MOV A, @0x0A ; tr10-> write “0xA” to port 3 MOV 0x0D, A JMP PORT2SCAN TR11: MOV A, @0x0B ; tr11-> write “0xB” to port 3 MOV 0x0D, A JMP PORT2SCAN TR12:...
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Page 95: Interrupt Subroutine
1. Set a suitable pre-scale ratio in IOC5. 2. Set the initial counter value in R1 for the TCC counter. 3. Set the TCC enable bit (TCIE) and global interrupt enable bit (ENI). Software Application • 87 EM60000 Series User’s Manual... -
Page 96: Mtc Timer Interrupt
Chapter 6 Process the interrupt subroutines in the following manner: 1. Save the value of the accumulator and status flag in RAM. Also save the control register value that will be modified by the subroutine. 2. Poll TCIF and check for the interrupt source. Assume it comes from TCC timer overflow. - Page 97 JMP TIMER_RET ; go to timer interrupt return MTCINT: COM 0x0D ; complement the port 3 output BC 0x05, 1 ; clear MTIF flag JMP TIMER_RET ; go to timer interrupt return Software Application • 89 EM60000 Series User’s Manual...
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Page 98: Speech Timer Interrupt
Chapter 6 NOTE Restoring the accumulator with a program that uses “MOV A, buffer” instruction, may affect the zero flag. Therefore, you must check the previously saved original status register value against the current one. Restore the correct zero flag if the value differs. 6.6.3 Speech Timer Interrupt As described in the Interrupts (Section 3.5 o f Chapter 3) and Special Function Control (Chapter 4) sections, the Speech Timer interrupts are controlled by the... -
Page 99: Example - Speech Interrupt
JBS 0x20, 0 ; if R11(0)=1 -> stop playing JMP WAIT ; else go to speech-ch1-set BC 0x0A, 0 ; disable speech interrupt BC 0x0A, 1 ; disable speech output to DAC Software Application • 91 EM60000 Series User’s Manual... -
Page 100: Voice Rom Access
RETS 6.7 Voice ROM Access As described in Chapter 4, Special Function Control, the EM60000 series provide two method of accessing voice ROM data. One is for speech data access and the other is for general-purpose voice ROM data access. For general-purpose voice ROM access, you should select the “Voice ROM access... -
Page 101: Playing Speech
7. Enable the output data to the DAC mixer by setting the SENA bit in the RA (MODE) register. 8. Enable the global interrupt (ENI), and enable the speech timer interrupt by setting the SENT bit in the RA (MODE) register. Software Application • 93 EM60000 Series User’s Manual... -
Page 102: Example - Simple Speech Playback (Pcm)
Chapter 6 9. Wait for the end-of-speech. If a stop condition is reached, then stop the playback procedure by disabling the speech interrupts. The following example is a simple PCM data playback demo. Assume the PCM data (8-bit signed data) starting address is 0x000000 in the voice ROM. Once playback is started, the main program will enter a loop and polls for an “active flag.”... - Page 103 JBC 0x03, 2 ; check zero flag JMP SCH1PCM_STOP ; if equal, go to stop playing MOV A, 0x21 ; not equal, write data to DAC IOW 0x0B ; write to DAC 1 RETS Software Application • 95 EM60000 Series User’s Manual...
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Page 104: Playing Melody
Chapter 6 SCH1PCM_STOP: BC 0x20, 4 ; set stop flag in R20 RETS 6.9 Playing Melody As explained in the chapter on Special Function Control (Chapter 4), four melody channels are provided for instrument melody playback. You can set up the Melody Function Control registers and use the MTC timer interrupt to handle the tempo, rhythm, and note data access. - Page 105 ; enable global INT WAIT: JBC 0x16, 0 ; check R16 for active flag JMP WAIT ; if active flag = 1, wait BC 0x05, 3 ; else, disable MTC timer interrupt OVER: JMP OVER Software Application • 97 EM60000 Series User’s Manual...
- Page 106 Chapter 6 ;---------------------------------------------------------- ; Melody INT subroutine ;---------------------------------------------------------- MELODY_INT: MOV A, 0x04 ; save RAM select register MOV 0x15, A MOV A, beat_counter JBS 0x03, 2 ; check beat counter = 0 or not JMP ENVELOPE ; not equal 0, go to do envelope READ_NEW_DATA: MOV A, @0x2 ;...
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Page 107: Power Down Mode
Port 2 input pins and no external devices is connected. 3. Set the other bi-directional ports as output, or connect external devices if they are configured as input ports. 4. Execute a “SLEP” instruction and enter sleep mode. Software Application • 99 EM60000 Series User’s Manual... -
Page 108: Example - Power Down And Wake Up By Input Port
Chapter 6 6.10.1 Example - Power Down and Wake Up by Input Port ;-------------------------------------------------------------- ; The example demonstrates the sleep and wakeup modes through Port ; 1. While initialized, enable Port 1 pull-low and set the other ; bi-directional ports as output to prevent extra current ;... - Page 109 SLEP ; enter sleep mode JMP INIT ; wake up and go to INIT TR3_DEBOUNCE: CALL DELAY20 ; debounce time 20 ms JBS 0x0B, 2 ; detect p1.2?=1: Y->p3.2=1 JMP SCAN N->scan Software Application • 101 EM60000 Series User’s Manual...
- Page 110 Chapter 6 TR3: MOV A, @0b00000100 MOV 0x0D, A SLEP ; enter sleep mode JMP INIT ; wake up and go to INIT TR4_DEBOUNCE: CALL DELAY20 ; debounce time 20 ms JBS 0x0B, 3 ; detect p1.3?=1: Y->p3.3=1 JMP SCAN N->scan TR4: MOV A, @0b00001000...
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