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ARM Prospector P1100 User Manual

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Prospector P1100
User Guide
ARM DUI 0122A

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Summary of Contents for ARM Prospector P1100

  • Page 1 Prospector P1100 User Guide ARM DUI 0122A...
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

  • Page 3: Electromagnetic Conformity

    Caution Changes or modifications not expressly approved by ARM Ltd. could void the user’s authority to operate this equipment. CE Declaration of Conformity Warning This is a class A product.
  • Page 4 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 5: Table Of Contents

    Setting the switches ..................2-3 Supplying power ................... 2-4 Removing the CPU module cover..............2-6 System startup ....................2-7 Chapter 3 Hardware Description SA-1100 CPU ....................3-2 System clocks ....................3-6 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 6 Flash memory expansion ................B-5 UCB1200 expansion..................B-6 FPGA and AC97 CODEC Interface.............. B-7 Connector support for expansion ..............B-8 PLD enhanced clocking................B-9 GPIO support for expansion ............... B-10 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 7 Relative merits of the active TFT screen options ........ 3-43 Table 3-21 LCD signal connectors ................ 3-44 Table 3-22 Power supply rail usage ..............3-47 Table 3-23 JTAG interface cable specification (Xilinx).......... 3-52 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 8 Table B-1 Power supply support for expansion ........... B-2 Table B-2 SPI chip select assignment ..............B-4 Table B-3 GPIO pins used to support system expansion ........B-10 Copyright © ARM Limited 2000. All rights reserved. viii ARM DUI 0122A...
  • Page 9 Figure 3-12 MMC interface..................3-37 Figure 3-13 Touch screen interface (ADS7843)............. 3-38 Figure 3-14 UCB1200 functional diagram .............. 3-39 Figure 3-15 JTAG architecture ................3-51 Figure 4-1 Keyboard controller message structure ..........4-20 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 10 SIB frame timing ................. 4-28 Figure 4-9 MMC command token ................ 4-31 Figure 4-10 ADS7843 SPI bus timing ..............4-35 Figure B-1 Modem and audio expansion connectors ..........B-8 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 11: Preface

    Preface This preface introduces the ARM Prospector P1100 and its reference documentation. It contains the following sections: • About this document on page xii • Further reading on page xv • Feedback on page xvi. Copyright © ARM Limited 2000. All rights reserved.

  • Page 12: About This Document

    About this document This document is the user guide for the Prospector P1100 development system. Intended audience This document has been written for system hardware and software developers of ARM-based products. Using this manual This document is organized into the following chapters:...

  • Page 13: Typographical Conventions

    Typographical conventions The following typographical conventions are used in this document: bold Highlights ARM processor signal names, and interface elements such as menu names. Also used for terms in descriptive lists, where appropriate. italic Highlights special terminology, cross-references and citations.
  • Page 14 Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 15: Further Reading

    Further reading This section lists publications by ARM Limited, and by third parties. ARM periodically provides updates and corrections to its documentation. See for current errata sheets and addenda. http://www.arm.com See also the ARM Frequently Asked Questions list at: http://www.arm.com/DevSupp/Sales+Support/faq.html...

  • Page 16: Feedback

    Feedback ARM Limited welcomes feedback both on the Prospector, and on the documentation. Feedback on the Prospector/P1100 If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • a concise explanation of your comments.
  • Page 17 Chapter 1 Introduction This chapter introduces the Prospector P1100 development system and contains the following sections: • About the Prospector P1100 on page 1-2 • System overview on page 1-4 • Software development tools on page 1-7. Copyright © ARM Limited 2000. All rights reserved.

  • Page 18: Chapter 1 Introduction

    Introduction About the Prospector P1100 The Prospector P1100 provides a flexible and portable StrongARM development and evaluation system. It enables you to work with a system that models your end product and allows you to realistically demonstrate your designs for mobile and hand-held applications.

  • Page 19: Figure 1-1 Prospector P1100 Expanded System

    Introduction CPU enclosure Keyboard/display enclosure Figure 1-1 Prospector P1100 expanded system Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 20: System Overview

    Introduction System overview Figure 1-1 shows the architecture of the Prospector P1100 system. Expansion connectors 16MB EDO FPGA 16MB EDO 8-64MB DRAM (option) DRAM flash (second bank) Expanded system options SA-1100 System controller (PLD) LCD screen ADS7843 touch screen controller...
  • Page 21 • touch screen controller • SPI expansion (option) • Multi Media Card (MMC) socket. Figure 1-3 on page 1-6 shows the layout of the CPU board upper surface. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 22: Figure 1-3 Cpu Board Layout (Top)

    Power supply jack 9V Battery input connector 3V UCB1200 FLASH IrDA Keyboard controller DRAM COM1 System controller (PLD) StrongARM COM2 processor (console) (SA-1100) Figure 1-3 CPU board layout (top) Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 23: Software Development Tools

    • ARM Firmware Suite (AFS) • ARM Developer Suite (ADS) evaluation copy 1.3.1 The ARM Firmware Suite (AFS) is a collection of low-level software and utilities which aid you to: • evaluate and benchmark ARM-based platforms • port operating systems and applications •...
  • Page 24 Introduction 1.3.2 ADS is a software development suite used for creating applications for the ARM architecture. The suite comprises: • Code generation tools – Embedded C++ and C compilers, assembler and linker for ARM and Thumb instruction sets • An integrated development environment for Windows – CodeWarrior® IDE from Metrowerks •...
  • Page 25 Interface connectors on page 2-2 • Supplying power on page 2-4 • Removing the CPU module cover on page 2-6 • Setting the switches on page 2-3 • System startup on page 2-7. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 26: Chapter 2 Getting Started

    Figure 2-1 shows the external interface connectors on the side of the motherboard enclosure. IrDA port COM1 COM2 Audio-in DC power supply (console) Audio-out Figure 2-1 External interface connectors Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 27: Setting The Switches

    Figure 2-2 BOOTSEL and DEVMODE switches The hexadecimal switch and remaining three elements within the DIL switch pack are intended for general purpose use (see LED control and switch sensing on page 3-20). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 28: Supplying Power

    Figure 2-3 on page 2-5. Note Systems fitted with a backlit display cannot be powered from batteries. The P1100 does not incorporate a battery charger. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 29: Figure 2-3 Battery Installation

    Replace the cap and re-secure by it turning it one quarter turn clockwise. The system powers up immediately. Note Battery provision is intended for experimentation with battery operation and power control rather than for continuous operation. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 30: Removing The Cpu Module Cover

    It is suggested that you remove the cover to make necessary adjustments and then replace the cover before operating the system. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 31: System Startup

    (known as hard vectors in the ARM Architecture Reference Manual). The SA-1100 maps these addresses to static memory, but these are remapped by the ARM Firmware Suite (AFS). The AFS carries out this remapping as part of the initialization sequence, remapping the hard vectors to DRAM for application use.
  • Page 32 DRAM before being executed. This enables the ARM Flash Utilities ( bootfu to reprogram flash. For details of the ARM Firmware Suite, refer to the ARM Firmware Suite Reference Guide. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 33 Philips UCB1200 codec and touch screen controller on page 3-39 • Display interface on page 3-43 • Distribution board on page 3-44 • Power supply on page 3-45 • JTAG interface on page 3-51. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 34: Sa-1100 Cpu

    16-entry minicache • memory management unit • write buffer. The SA-1100 is software compatible with the ARM v4 architecture. In addition to the processor core, the SA-1100 incorporates system support modules: • memory and PCMCIA controller — supporting EDO DRAM, and SRAM or flash —...

  • Page 35: Figure 3-1 Sa-1100 Block Diagram

    IrDA port • MCP port • Serial Peripheral Interface (SPI) port. For descriptions of these serial ports and their implementation in the P1100 design, see Serial interfaces on page 3-26. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 36: Table 3-1 Sa-1100 Gpio Pin Assignment

    Output SPI bus – frame GPIO14 CPU_SPI_CS0 Output SPI encoded chip select 0 GPIO15 CPU_SPI_CS1 Output SPI encoded chip select 1 GPIO16 CPU_SPI_CS2 Output SPI encoded chip select 2 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 37 Buffered core frequency/2 clock GPIO27 CPU_32KHz* Buffered untrimmed 32kHz clock Note Signals marked with * in Table 3-1 require the Test Unit Control Register (TUCR) set up in the SA-1100. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 38: System Clocks

    GPIO27. An RTC derived 1Hz signal appears on GPIO25. The clocks available from GPIO pins are under software control (see GPIO pin assignment on page 3-4). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 39 In addition to the SA-1100 derived clocks, a 4 MHz ceramic resonator is used to drive the on-chip oscillator within the keyboard controller (see Keyboard controller on page 3-32). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 40: Reset Control

    The architecture of the reset control subsystem is illustrated in Figure 3-3. MST_nRST EconoReset System Keyboard PLD_nRST_OUT controller controller SYSTEM_nRESET CPU_nRESET_OUT JP17 UCB1200 SA-1100 BUF_JTAG_nRESET FPGA (option) Multi-ICE connector (JTAG) Figure 3-3 Reset system architecture Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 41: Table 3-2 Reset Signal Summary

    LOW until the PLD_nRST_OUT PLD is initialized. The CPU asserts while CPU_nRESET_OUT PLD_nRST_OUT asserted, and keeps it asserted until the PLD releases PLD_nRST_OUT Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 42 Sleep reset is invoked when the SA-1100 enters sleep mode, either by software setting the force sleep bit in the power manager control register or by a power supply fault. is asserted, and the DRAMs placed in self refresh mode. CPU_RESET_OUT Copyright © ARM Limited 2000. All rights reserved. 3-10 ARM DUI 0122A...

  • Page 43: System Controller Pld

    Figure 3-4 System controller PLD functional block diagram A JTAG interface is provided for in system programming (ISP). Please see the section on JTAG for programming details. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-11...

  • Page 44: Figure 3-5 Interrupt Controller

    COM2_RDY COM2 COM2_SENSE (MAX3225) PLD_COM1 COM1_RDY COM1 CPU_GPIO1 COM1_SENSE (MAX3225) CPU_GPIO0 PLD_CODEC CDC_IRQ3 CDC_IRQ2 CODEC CDC_IRQ1 (FPGA option) CDC_IRQ0 UCB_IRQ UCB1200 Keyboard KEY_nATTN controller Figure 3-5 Interrupt controller Copyright © ARM Limited 2000. All rights reserved. 3-12 ARM DUI 0122A...

  • Page 45: Table 3-3 Interrupt Summary

    These are low priority interrupts generated when the serial port has valid signal levels and is ready for communication. This is not to be confused with the serial port handshake signals. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-13...
  • Page 46 PLD senses S4 and S5 to support the following functions: is the BOOTSEL switch. It is used by the boot monitor component of the ARM Firmware Suite (AFS) to select between the default or alternative boot image. If you are not using AFS, this switch can be assigned another meaning.

  • Page 47: Figure 3-6 Power Output Control

    PLD_LCDBC register are used to vary the monochrome bias output LCD_OUT4 PLD_LCDEN PLD_LCDON PLD_LCDBC 14-20V PLD_LCD_UP MAX686 LCD_OUT4 PLD_LCD_DN PLD_PWR ALT_SUPPLY_SIG PLD_MODE LCD_OUT2 MAX863 PLD_S4_ON PLD_S3_ON PLD_S2A_ON PLD_S1_OFF LCD_OUT1 MAX1703 LCD_OUT3 Figure 3-6 Power output control Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-15...

  • Page 48: Table 3-4 Lcd Power Configurations

    The state of the sense line can be read from this bit in the power control register (see Power control register on page 4-14). Copyright © ARM Limited 2000. All rights reserved. 3-16 ARM DUI 0122A...

  • Page 49: Figure 3-7 Interface Control

    These are controlled by PLD registers (see System controller PLD registers on page 4-13). The signals controlled by the PLD are summarized in Table 3-5 on page 3-18. Writing a 1 to the relevant bit enables the signal. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-17...

  • Page 50: Table 3-5 Interface Enable

    0x10000000 FLASH_nCS4 Expansion connector 0x12000000 FLASH_nCS5 Expansion connector 0x13000000 FLASH_nCS6 FPGA 0x08000000 Note are routed to the expansion connector. is routed CPU_nCS1 CPU_nCS2 CPU_nCS3 to the optional FPGA Copyright © ARM Limited 2000. All rights reserved. 3-18 ARM DUI 0122A...
  • Page 51 ). These are connected to the auxiliary PLD_GPIO[2:0] connector for the optional FPGA and can be controlled by accessing the PLD input/output register (see Software input/output control register on page 4-16). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-19...

  • Page 52: Led Control And Switch Sensing

    Two additional LEDs provide status indication for the SA-1100 and FPGA, if fitted. Figure 3-8 shows the LED control and switch reader. System controller Keyboard controller Figure 3-8 LEDs and switches Copyright © ARM Limited 2000. All rights reserved. 3-20 ARM DUI 0122A...

  • Page 53: Table 3-7 Leds Connection And Control

    Three switches within the DIL pack and the rotary switch are connected to the GPIO pins on the keyboard controller. These switches can be assigned any meaning by the software developer. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-21...

  • Page 54: Table 3-8 Switch Connections And Assignment

    (see Boot and mode control on PLD_BOOTSEL AFS boot control page 3-14) Rotary hex Keyboard controller GIO[17:14] Supplies a 1’s compliment 4-bit value. Function of this switch is user definable. Copyright © ARM Limited 2000. All rights reserved. 3-22 ARM DUI 0122A...

  • Page 55: Memory Subsystem

    Figure 3-9 on page 3-24 shows the architecture of the Flash memory. To aid clarity the diagram does not show the data and address buffers, or the output enables and write enable signals. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-23...

  • Page 56: Figure 3-9 Flash Memory Block Diagram

    HIGH to avoid it floating and wasting unnecessary power. Each flash chip contains sixty-four 128KB blocks. These can be programmed and erased independently using flash tools and utilities provided by the ARM Firmware Suite (see the ARM Firmware Suite Reference Guide).

  • Page 57: Table 3-9 Maximum Dram Current

    CPU_MEM_nOE This signal enables the data output buffers on read cycles when asserted (LOW). CPU_MEM_nWE This signal indicates a write cycle when asserted (LOW). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-25...

  • Page 58: Serial Interfaces

    COM2 transceiver GPIO_20 is configured as an input for the UART1_CTS line. This line is asserted by the connected device and should be set to interrupt the SA-1100 Copyright © ARM Limited 2000. All rights reserved. 3-26 ARM DUI 0122A...
  • Page 59 30 seconds. The power-down mode can be overridden by asserting the signal. PLD_COM1_EN The MAX3225 is powered from the non-switched +3V rail. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-27...

  • Page 60: Spi Bus

    SA-1100 GPIO[13:10] and is allows both types of serial interface to be supported at the same time. See the Intel StrongARM SA-1100 Microprocessor Developer’s Manual for further information. Copyright © ARM Limited 2000. All rights reserved. 3-28 ARM DUI 0122A...

  • Page 61: Figure 3-10 Spi Bus Architecture

    The architecture of the SPI bus on P1100 CPU board is shown in Figure 3-10. Keyboard ADS7843 (socket 1) controller CPU_SPI_SCLK CPU_SPI_RXD SA-1100 CPU_SPI_TXD CPU_SPI_CS[2:0] 3-to-8 decoder System PLD_SPI_nEN & controller PLD_SPI_nCS[7:0] Figure 3-10 SPI bus architecture Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-29...

  • Page 62: Table 3-14 Spi Signal Summary

    The decoder is enabled and disabled by a signal from the system controller PLD. This signal is controlled by the bit in the SPI enable register (see SPI decoder enable SPI_EN register on page 4-16. Copyright © ARM Limited 2000. All rights reserved. 3-30 ARM DUI 0122A...

  • Page 63: Table 3-15 Spi Chip Select Assignment

    The MMC interface timing requirements are described in MMC transaction timing on page 4-33. • The touch screen controller timing requirements are described in Programming the touch screen controller on page 4-34. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-31...

  • Page 64: Keyboard Controller

    4MHz crystal KEY_nATTN controller ROW[7:0] Keyboard controller COL[15:0] PS/2 GIO0x/LEDx GIO1x/SW1x Current Onboard Onboard sensing LEDs switches JP38 JP39 JP40 Mouse Keyboard Keyboard pointer LEDs Figure 3-11 Keyboard controller Copyright © ARM Limited 2000. All rights reserved. 3-32 ARM DUI 0122A...
  • Page 65 Each bit has a high current sink capability (20mA peak, 15mA average). On system units, these ports are also used to control the LEDs on the distribution board which Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 66: Table 3-16 Keyboard Controller Gpio/Led Assignment

    The P1100 provides a number of switches that can be read from keyboard controller internal registers: • DIL (three switches from a bank of five) • hexadecimal rotary switch • external switch (wired through JP11) • lid switch (wired through JP9) Copyright © ARM Limited 2000. All rights reserved. 3-34 ARM DUI 0122A...

  • Page 67: Table 3-17 Keyboard Controller Gpio Port Assignments

    3V shunt – source sample used for the current measuring circuitry. GIO32 and GIO33 are connected to the DF13 style connector, JP1. GIO32/AD2 Expansion – JP1 GIO33/AD3 Expansion – JP1 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-35...

  • Page 68: Table 3-18 Power Management States

    PLD (open drain nWKUP buffer turned OFF). When the PLD shuts down the keyboard, only the software selected wake up keys can re-activate it. Copyright © ARM Limited 2000. All rights reserved. 3-36 ARM DUI 0122A...

  • Page 69: 3.10 Mmc Interface

    The cards and connectors are keyed to prevent incorrect insertion. The +3V supply is permanently enabled. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-37...

  • Page 70: 3.11 Touch Screen Controller

    PENIRQ bit in the interrupt flag CPU_GPIO[1] register. Information about programming the device and timing for the SPI bus are provided in Programming the touch screen controller on page 4-34. Copyright © ARM Limited 2000. All rights reserved. 3-38 ARM DUI 0122A...

  • Page 71: Philips Ucb1200 Codec And Touch Screen Controller

    Figure 3-14 UCB1200 functional diagram The UCB1200 is programmed using the Serial Interface Bus (SIB), which is provided by the MCP port of the SA-1100 (see Programming the UCB1200 on page 4-27). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-39...
  • Page 72 The distribution board devices are disconnected if external devices are connected into the jack sockets. The connector JP48 provides a +3V power source for active microphones. Copyright © ARM Limited 2000. All rights reserved. 3-40 ARM DUI 0122A...

  • Page 73: Table 3-19 Ucb1200 Gpio Pin Assignments

    DAA off hook signal UCB_DAA_RI DAA ring indicator UCB_DAA_MUTE DAA mute signal IO[5:0] UCB_LED[5:0] General purpose input/output. These are connected to the dual row 10-pin DF13 type connector, JP2. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-41...
  • Page 74 The touch screen inputs are described in Touch screen controller on page 3-40. Conversions are synchronized by signal . This is controlled by the IO9 UCB_ADCSYNC pin from the general purpose input/output block. Copyright © ARM Limited 2000. All rights reserved. 3-42 ARM DUI 0122A...

  • Page 75: 3.13 Display Interface

    5bits. This requires1-bit of 2 of the colors to be tied either high or low. The best compromise is to tie the LSB of the red and blue low. This gives good colors and acceptable blacks to whites. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-43...

  • Page 76: 3.14 Distribution Board

    The micro joystick used in the P1100 design is the MicroModule, part number VP5510. This is a compact button style joystick providing 2-button mouse functionality. Copyright © ARM Limited 2000. All rights reserved. 3-44 ARM DUI 0122A...

  • Page 77: 3.15 Power Supply

    The IRF7304 U38 is used for power source selection (external PSU or battery) by a hardware controlled signal • The IRF7304 U46 are to switch the +9V backlight inverter supply LCD_OUT3 and the switched + 3V3 LCD supply LCD_OUT2 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-45...
  • Page 78 You can also wire your own battery holder to JP33. Caution Take great care to connect the battery with the correct polarity. The positive pin (JP33 pin 2) is closest to the edge of the board. Copyright © ARM Limited 2000. All rights reserved. 3-46 ARM DUI 0122A...

  • Page 79: Table 3-22 Power Supply Rail Usage

    LCD_OUT3 External power supply. +9V used to power the backlight inverter in a transmissive color LCD configuration. Controlled by the PLD_S3_ON bit in the PLD power control register. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-47...
  • Page 80 CRITICAL SUSPEND mode. It exits CRITICAL SUSPEND when is asserted. PSU_BATT_OK an inverted version of which is supplied to the PSU_VDD_FLT PSU_BATT_OK SA-1100. When asserted the SA-1100 enters sleep mode. Copyright © ARM Limited 2000. All rights reserved. 3-48 ARM DUI 0122A...
  • Page 81 Enable wake-up keys on the keyboard controller. Flush SA-1100 Dcaches and save the processor context into memory Place DRAMs into self refresh mode Place the SA-1100 into sleep mode Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-49...
  • Page 82 To wake from sleep mode: Restore the SA-1100 configuration registers and any system context. Take the DRAM out of self refresh mode. Re-initialize and power up the LCD. Copyright © ARM Limited 2000. All rights reserved. 3-50 ARM DUI 0122A...

  • Page 83: 3.16 Jtag Interface

    Multi-ICE. A small profile, single row 8-way vertical DF13 type connector (JP18) provides the JTAG external interface. An ARM supplied programming utility can be used to program the PLD using Multi-ICE. An SA-1100 boundary scan utility is supplied to enable you to program the flash.

  • Page 84: Table 3-23 Jtag Interface Cable Specification (Xilinx)

    The Xilinx cable specification is shown is Table 3-23. Table 3-23 JTAG interface cable specification (Xilinx) JP18 pin connector Function (P1100) 18,19,20,21 The ARM Multi-ICE cable specification is shown in Table 3-24. Table 3-24 Multi-ICE cable specification Multi-ICE JP18 pin connector Function (P1100)
  • Page 85 Hewlett Packard HP16xxx series logic analyzer. The primary function of each connector is: • JP34: SA-1100 address bus • JP35: SA-1100 data bus • JP36: SA-1100 and PLD generated system control signals. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 3-53...
  • Page 86 Hardware Description Copyright © ARM Limited 2000. All rights reserved. 3-54 ARM DUI 0122A...
  • Page 87 Programming the keyboard controller on page 4-20 • Programming the UCB1200 on page 4-27 • MMC programming on page 4-31 • Programming the touch screen controller on page 4-34. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 88: About This Chapter

    The registers for devices, such as those in the SA-1100, are listed for convenience, but you should refer to the documentation supplied by the device manufacturers for detailed information. See Other publications on page -xv. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 89: Memory Map

    The static bank select regions are used to support accesses to the flash memory, system controller PLD internal registers, and expansion space. The system controller PLD encodes three of the bank select signals (CPU_nCS[2:0]) from the CPU and Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 90: Table 4-2 Static Memory Region Memory Map

    For more information about how the flash chip selects are generated, see Flash chip-select control on page 3-18. 4.2.2 PCMCIA socket 1:0 This region is mapped conventionally. There are no PCMCIA devices on the P1100 CPU board. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 91: Table 4-3 Peripheral Module Registers

    Peripheral module registers The peripheral module registers are summarized in Table 4-3. The notes column indicates required values and the default values set by the ARM Firmware Suite, where appropriate. Detailed descriptions of these registers can be found in the Intel StrongARM SA-1100 Microprocessor Developer’s Guide.
  • Page 92 Bit 5 Receive Clock Edge Select Bit 6 Transmit Clock edge Select UART3 Control Register 1 Bit 0-3 Baud Rate Divisor 0x8005 0004 UART3 Control Register 2 Bit 0-7 Baud Rate Divisor 0x8005 0008 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 93 SPI bus (SSP – serial channel 4) SSP Control Register 0 Bit 0-3 Data Size Select 0x8007 0060 Bit 4-5 Frame Format Bit 7 Synchronous Serial Port Enable Bit 8-15 Serial Clock Rate Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 94: Table 4-4 System Controller Module Registers

    OS Timer Match Register 3 0x9000 000C OS Timer Counter Register 0x9000 0010 OS Timer Status Register 0x9000 0014 OS Timer Watchdog Enable Register 0x9000 0018 OS Timer Interrupt Enable Register 0x9000 001C Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 95 Bit 16:14 encoded SPI chip select Bit 17 UART1 RTS Status Bit 18 UART1 CTS Status Bit 19 UART2 RTS Status Bit 20 UART2 CTS Status Bit 25 CPU LED Status Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 96 Bit 10 SSP Transmit Bit 11 SSP Receive Bit 12 SSP Clock Bit 13 SSP Frame Bit 21 MBGNT Bit 22 MBREQ Bit 26 RCLK Out Bit 27 32KHz Out Copyright © ARM Limited 2000. All rights reserved. 4-10 ARM DUI 0122A...

  • Page 97: Table 4-5 Memory And Expansion Registers

    This group of registers is used to configure the memory and expansion interfaces of the SA-1100. These are set up by the ARM Firmware Suite. Detailed descriptions of these registers can be found in the Intel StrongARM SA-1100 Microprocessor Developer’s Guide.

  • Page 98: Table 4-6 Lcd Control Registers

    LCD controller registers This set of registers is used to configure and control the display interface. These are set up by ARM Firmware Suite, where appropriate. Detailed descriptions of these registers can be found in the Intel StrongARM SA-1100 Microprocessor Developer’s Guide...

  • Page 99: System Controller Pld Registers

    Bits are set to ‘1’ to indicate an active interrupt from the associated source • multiple interrupts result in multiple flags being set • interrupt flags are cleared by clearing the interrupt request from the source device. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-13...

  • Page 100: Table 4-8 Pld Interrupt Flag Register

    Power control register The power control register, PLD_PWR (0x10000004), is used to: • enable LCD power supplies • select the power supply operating mode • detect an external power supply Copyright © ARM Limited 2000. All rights reserved. 4-14 ARM DUI 0122A...

  • Page 101: Table 4-9 Pld Power Control Register

    The keyboard control register, PLD_KBD (0x10000008), contains two active bits, as shown in Table 4-10. Table 4-10 PLD keyboard control register Name Function KBD_WAKE Keyboard wakeup KBD_EN Enables the keyboard controller Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-15...

  • Page 102: Table 4-11 Pld Input/Output Register

    The IrDA enable register, PLD_IrDA (0x10000014), contains one active bit (bit 0) which is used to enable/disable the IrDA port transceiver. • 0 = IrDA port disabled • 1 = IrDA port enabled. Copyright © ARM Limited 2000. All rights reserved. 4-16 ARM DUI 0122A...

  • Page 103: Table 4-12 Pld Com2 Enable Register

    COM1 caused the COM1 interrupt indicated by the PLD_INT register. COM1_EN This bit is used to enable/disable the COM2 port transceiver: 0 = disabled 1 = enabled Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-17...

  • Page 104: Table 4-14 Fpga Codec Register

    The LCD enable register, PLD_LCDEN (0x10400008), contains one active bit (bit 0) used to switch a monochrome display ON or OFF, when fitted. Write a 1 to enable the LCD display, write a 0 to disable the LCD display. Copyright © ARM Limited 2000. All rights reserved. 4-18 ARM DUI 0122A...

  • Page 105: Table 4-16 Gpio Register

    PENIRQ interrupt, and then commence transactions with the ADS7843. When the transaction is complete, write a 0 to TCH_EN to disable the interface and re-enable the PENIRQ interrupt. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-19...

  • Page 106: Programming The Keyboard Controller

    1 and 32 bytes of data. Figure 4-1 shows the general structure of messages. Protocol header Message/report identifier Message body (if required) Figure 4-1 Keyboard controller message structure Copyright © ARM Limited 2000. All rights reserved. 4-20 ARM DUI 0122A...

  • Page 107: Table 4-18 Message Type Summary

    The first byte of message body for read block and report block message types indicates a the number data bytes contained in the message body. The body length can vary between 2 and 32 bytes. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-21...

  • Page 108: Figure 4-2 Ur8Hc007 Register Organization

    Individual registers in the bank are selected by the register offset value contained in the message, as shown Figure 4-1 on page 4-20. Note For a full description of the keyboard controller registers, see the Technical Reference Manual USAR Keyboard controller. Copyright © ARM Limited 2000. All rights reserved. 4-22 ARM DUI 0122A...

  • Page 109: Figure 4-3 Spi Master Timing: Host Writes To The Keyboard Controller

    PLD_SPI_nCS0. The keyboard controller responds by asserting KEY_nATN and driving CPU_SPI_RXD HIGH. • The host must wait a minimum of 0.1ms and a maximum of 5ms before beginning to transfer the first byte. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-23...

  • Page 110: Figure 4-4 Spi Slave Timing: Keyboard Controller To Host

    Figure 4-4 SPI slave timing: keyboard controller to host Keyboard controller transfers to the host are as follows: • The keyboard controller alerts the host by asserting KEY_nATN and driving CPU_SPI_RXD high. Copyright © ARM Limited 2000. All rights reserved. 4-24 ARM DUI 0122A...

  • Page 111: Figure 4-5 Keyboard Data Report

    Input may also be from an external keyboard device connected to J19. Figure 4-5 shows the format of a keyboard data report. Header = 0x88 Key number Figure 4-5 Keyboard data report Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-25...

  • Page 112: Figure 4-6 Pointing Device Report

    PS/2 device. Figure 4-7 shows the format of a report block. Header = 0x85 Register offset Block length Port status Figure 4-7 Report block JP19 can used to connect an external mouse and keyboard. Copyright © ARM Limited 2000. All rights reserved. 4-26 ARM DUI 0122A...

  • Page 113: Programming The Ucb1200

    15:0 Audio input path data [15:0] Audio output path data [15:0] bit 0 = MSB bit 0 = MSB 12 MSB bits are read bits [15:12] are 0 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-27...

  • Page 114: Table 4-20 Ucb1200 Register Summary

    Table 4-20 UCB1200 register summary Address Name Null register Reserved Mode register ID register ADC data register ADC control register Touch screen control register Audio control register B Copyright © ARM Limited 2000. All rights reserved. 4-28 ARM DUI 0122A...
  • Page 115 Bit 1 in the PLD interrupt register is a 1 if the UCB1200 is the source of the pending interrupt. The UCB1200 provides the following interrupt sources: • 10 input/output pins Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-29...
  • Page 116 • tspx_low • tsmx_low These sources are enabled, acknowledged and cleared by accessing the interrupt rising and falling edge registers and the interrupt status/clear register within the UCB1200. Copyright © ARM Limited 2000. All rights reserved. 4-30 ARM DUI 0122A...

  • Page 117: Mmc Programming

    CPU_SPI_TXD when written to the card. Data transfers always use multiples of 8 bits on the SPI bus which are byte aligned to the chip select signal Content Figure 4-9 MMC command token Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-31...

  • Page 118: Table 4-21 Mmc Register In Spi Mode

    CMD17 READ_SINGLE_BLOCK Read a single block CMD27 PROGRAM_CSD Protect writable bits in CSD register CMD28 SET_WRITE_PROT Protection ON for addressed group CMD29 CLR_WRITE_PROT Protection OFF for dressed group Copyright © ARM Limited 2000. All rights reserved. 4-32 ARM DUI 0122A...
  • Page 119 (see Keyboard controller host interface timing on page 4-23), although the way that data is assembled into valid messages is entirely different. For more detailed timing requirements, refer to the documentation supplied by your card vendor. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-33...

  • Page 120: Programming The Touch Screen Controller

    PENIRQ is enabled 01 = Power down between conversions. PENIRQ is disabled. 10 = Reserved. 11 = Device is always powered. Copyright © ARM Limited 2000. All rights reserved. 4-34 ARM DUI 0122A...

  • Page 121: Figure 4-10 Ads7843 Spi Bus Timing

    As soon as it has enough data (after the first five bits), the ADS7843 begins to acquire a sample. • The CPU begins to read the conversion data on the 9th clock, starting with the MSB. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A 4-35...
  • Page 122 The SPI bus timing for the ADS7843 differs from that used for the keyboard controller in that for the ADS7843 CPU_SPI_SCLK idles LOW and is sampled on the rising edge. Copyright © ARM Limited 2000. All rights reserved. 4-36 ARM DUI 0122A...

  • Page 123: Appendix A Connector Reference

    UCB1200 DAA (modem) interface – JP37 on page A-13 • Distribution panel connectors on page A-14. Note The abbreviation NC used in the tables in this appendix means not connected. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 124: Table A-1 P1100 Connector Summary

    LCD backlight JP23 DF9-31P-1V LCD TFT 16bpp color JP24 DF13-15P-125H LCD STN monochrome JP26 DF13-40DP-125V FPGA IO support JP27 0.1" HDR1x3 FPGA/AC97 3V select JP28 0.1" HDR1x2 AC97 mono select Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 125 StereoJack External headphones JP48 0.1" HDRx2 Microphone power JP49 StereoJack AC97 audio JP50 0.1" HDR1x11 AC97 header JP51 StereoJack AC97 audio JP53 StereoJack AC97 audio JP56 RJ11 AC97 modem Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 126: Ucb1200 Touchscreen Interface - Jp3

    UCB1200 Touchscreen Interface – JP3 Table A-2 shows the pinout of JP3. Table A-2 JP3 pinout Function UCB_TSPY (Positive Y) UCB_TSPX (Positive X) UCB_TSMY (Negative Y) UCB_TSMX (Negative X) Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 127: Table A-3 Jp14 Pinout

    Connector reference MMC Connector – JP14 Table A-3 shows the pinout of JP14. Table A-3 JP14 pinout Function PLD_SPI_nCS1 BUF_SPI_TXD BUF_SPI_CLK BUF_SPI_RXD Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 128: Ads7843 Touchscreen Interface - Jp15

    Connector reference ADS7843 Touchscreen Interface – JP15 Table A-4 shows the pinout of JP15. Table A-4 JP15 pinout Function Positive Y Positive X Negative Y Negative X Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 129: Table A-5 Jp18 Pinout

    Connector reference JTAG Interface connector – JP18 Table A-5 shows the pinout of JP18. Table A-5 JP18 pinout Function JTAG_nRESET BUF_PLD_TDO JTAG_TMS JTAG_TDI JTACK_TCK SYSTEM_nRESET Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 130: Auxiliary Ps2 Interface - Jp19

    Auxiliary PS2 Interface – JP19 Table A-6 shows the pinout of JP19. Table A-6 JP19 pinout Function PS2_0DAT PS2_EN PS2_0CLK PS2_IDAT (Internal PS2 device) PS2_1DAT PS2_ICLK (Internal PS2 device) PS2_1CLK Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 131: Table A-7 Jp21 Pinout

    Connector reference Auxiliary SPI Interface Connector – JP21 Table A-7 shows the pinout of JP21. Table A-7 JP21 pinout Function Function BUF_SPI_RXD PLD_SPI_nCS7 PLD_SPI_nCS5 PLD_SPI_TXD PLD_SPI_nCS6 BUF_SPI_CLK PLD_SPI_nCS4 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 132: Table A-8 Jp23 Pinout

    LCD_DD_15 (Red 5) LCD_BIAS (ENAB) +3V3 LCD_DD_5 (Green 0) +3V3 LCD_DD_6 (Green 1) Tied HIGH (Horizontal Display Mode) LCD_DD_7 (Green 2) Tied HIGH (Vertical Display Mode ) LCD_DD_8 (Green 3) Copyright © ARM Limited 2000. All rights reserved. A-10 ARM DUI 0122A...

  • Page 133: Table A-9 Jp30 Pinout

    Table A-9 shows the pinout of JP30. Table A-9 JP30 pinout Function UART1_RXD CPU_UART1_TXD CPU_UART1_RTS UART1_CTS A.9.2 COM2 – JP31 Table A-10 shows the pinout of JP31. Table A-10 JP31 pinout Function UART2_RXD CPU_UART2_TXD Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A A-11...
  • Page 134 Connector reference Table A-10 JP31 pinout (continued) Function CPU_UART2_RTS UART2_CTS Copyright © ARM Limited 2000. All rights reserved. A-12 ARM DUI 0122A...

  • Page 135: A.10 Ucb1200 Daa (Modem) Interface - Jp37

    Table A-11 shows the pinout of JP37. Table A-11 JP37 pinout Function AGND UCB_TOUTP (Telephone Out Positive) UCB_TINP (Telephone In Positive) UCB_DAA_OH (Off Hook) UCB_DAA_MUTE (Mute) UCB_DAA_RI (Ring Indicate) Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A A-13...

  • Page 136: A.11 Distribution Panel Connectors

    Table A-12 shows the pinout of JP38. The connector provides the keyboard row signals and speaker connections. Table A-12 JP38 pinout Function KBD_ROW6 UCB_SPKR_P UCB_SPKR_N KBD_COL15 KBD_COL14 KBD_COL13 KBD_ROW7 KBD_ROW5 KBD_ROW4 KBD_ROW3 KBD_ROW2 KBD_ROW1 KBD_ROW0 Copyright © ARM Limited 2000. All rights reserved. A-14 ARM DUI 0122A...

  • Page 137: Table A-13 Jp39 Pinout

    Table A-13 shows the pinout of JP39. The connector provides the keyboard column signals. Table A-13 JP39 pinout Function KBD_COL12 KBD_COL11 KBD_COL10 KBD_COL9 KBD_COL8 KBD_COL7 KBD_COL6 KBD_COL5 KBD_COL4 KBD_COL3 KBD_COL2 KBD_COL1 KBD_COL0 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A A-15...

  • Page 138: Table A-14 Jp40 Pinout

    Table A-14 shows the pinout of JP40. The connector provides signals for the LEDs, mouse pointer, and reset button in the keyboard housing. Table A-14 JP40 pinout Function SYSTEM_nRESET PLD_nRST_OUT PS2_EN PS2_ICLK PS2_IDAT CPU_GPIO25 KBD_LED3 KBD_LED2 KBD_LED1 KBD_LED0 Copyright © ARM Limited 2000. All rights reserved. A-16 ARM DUI 0122A...

  • Page 139: Table A-15 Jp42 Pinout

    Connector reference A.11.4 Microphone connector – JP42 Table A-15 shows the pinout of JP42. Table A-15 JP42 pinout Function UCB_MIC_GND UCB_MIC +5V0 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A A-17...
  • Page 140 Connector reference Copyright © ARM Limited 2000. All rights reserved. A-18 ARM DUI 0122A...
  • Page 141 FPGA and AC97 CODEC Interface on page B-7 • Connector support for expansion on page B-8 • PLD enhanced clocking on page B-9 • GPIO support for expansion on page B-10. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 142: Appendix B System Expansion Options

    100mA 200mA 3600mW 200mA 100mA 100mA These figures can vary with the number of items within the P1100 system that are active and should be used for guidance only. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 143: System Expansion

    • PCMCIA control signals • GPIO • buffered address and data buses • system control signals and DRAM strobes. Note This connector is not fitted as standard. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 144: Spi Expansion

    Note The chip select signal is reserved as a null select and should not be used PLD_SPI_nCS7 for expansion (see Using the SPI chip selects on page 3-30). Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 145: Flash Memory Expansion

    The buffered address and data busses along with PLD control outputs are routed to the expansion connector JP20. This allows connection of additional ROM/Flash or provision for an alternate boot path. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 146: Ucb1200 Expansion

    The interface uses GPIO pins to provide Mute, Ring Indicate (RI) and Off Hook (OH) signals. Connection is made at a single dual row 10-pin DF13 type connector, JP37. Note The connector JP37 is not fitted as standard. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 147: Fpga And Ac97 Codec Interface

    Three stereo 3.5mm jack sockets and an RJ11 telephone socket are positioned on the CPU board and connected to a header to allow a hard wired connection to the miniature input/output connector found on MDC cards. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 148: Connector Support For Expansion

    JP50 and enable you to connect, for example, an audio codec and modem that you have added to the system. Figure B-1 Modem and audio expansion connectors Note These connectors are not fitted on the standard product variant. Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 149: Pld Enhanced Clocking

    If an anhanced clocking device is used then these pins can be used. The pins affected by this are: • pin 92 – CDC_IRQ0 • pin 83 – CPU_RCLK_OUT • pin 37 – CPU_32KHz Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

  • Page 150: Table B-3 Gpio Pins Used To Support System Expansion

    CPU_MEMGNT GPIO1 CPU_GPIO1 This signal is routed to the expansion connector, J26. It can be used to generate interrupts to the SA-1100 (see Interrupt control on page 3-12). Copyright © ARM Limited 2000. All rights reserved. B-10 ARM DUI 0122A...
  • Page 151 ARM v4 architecture Asynchronous serial ports 3-26 Audio codec 3-40 Audio connector, expansion CE Declaration of Conformity Chip selects, SPI bus 3-30 CODEC enable and IRQ register 4-18 Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A Index-i...
  • Page 152 IrDA enable register 4-16 Expansion MCP signal summary 3-28 IrDA port 1-5, 3-28 Memory and expansion registers 4-11 system Memory map External connections for expansion Memory subsystem 3-23 Index-ii Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...
  • Page 153 Serial interfaces 3-26 PLD version register 4-19 System startup Serial ports PLD, system controller System wakeup 3-13, 3-50 PLD_CODEC 4-18 frame format 4-27 PLD_COM1 4-17 frame timing 4-28 ARM DUI 0122A Copyright © ARM Limited 2000. All rights reserved. Index-iii...
  • Page 154 3-39 UCB1200 GPIO pin assignments 3-41 UCB1200 interrupts 4-29 UCB1200 registers 4-28 Using the GPIO pins, UCB1200 4-29 Wakeup 3-13 Watchdog reset 3-8, 3-10 Xilinx cable specification 3-52 Index-iv Copyright © ARM Limited 2000. All rights reserved. ARM DUI 0122A...

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