Table of Contents
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Product List .......................................................................................................................................................................... 3
Description ........................................................................................................................................................................... 3
Features............................................................................................................................................................................... 3
Pin Configuration ................................................................................................................................................................. 4
Block Diagram...................................................................................................................................................................... 5
Pin Description..................................................................................................................................................................... 6
Special Function Register (SFR) ......................................................................................................................................... 7
Function Description .......................................................................................................................................................... 10
1.
General Features ........................................................................................................................................................ 10
1.1.
Embedded Flash .......................................................................................................................................... 10
1.2.
IO Pads ........................................................................................................................................................ 10
1.3.
Instruction timing Selection .......................................................................................................................... 10
1.4.
The Clock Output Selection ......................................................................................................................... 10
1.5.
RESET ..........................................................................................................................................................11
1.5.1.
Hardware RESET function ...............................................................................................................11
1.5.2.
Software RESET function ................................................................................................................11
1.5.3.
Reset status .....................................................................................................................................11
1.5.4.
Time Access Key register (TAKEY)................................................................................................. 12
1.5.5.
Software Reset register (SWRES).................................................................................................. 12
1.5.6.
Example of software reset .............................................................................................................. 12
1.6.
Clocks .......................................................................................................................................................... 12
2.
Instruction Set ............................................................................................................................................................. 13
3.
Memory Structure ........................................................................................................................................................ 17
3.1.
Program Memory ......................................................................................................................................... 17
3.2.
Data Memory................................................................................................................................................ 18
3.2.1.
Data memory - lower 128 byte (00h to 7Fh) ................................................................................... 18
3.2.2.
Data memory - higher 128 byte (80h to FFh) ................................................................................. 18
4.
CPU Engine................................................................................................................................................................. 19
4.1.
Accumulator ................................................................................................................................................. 19
4.2.
B Register .................................................................................................................................................... 19
4.3.
Program Status Word................................................................................................................................... 20
4.4.
Stack Pointer ................................................................................................................................................ 20
4.5.
Data Pointer ................................................................................................................................................. 20
4.6.
Data Pointer 1 .............................................................................................................................................. 21
4.7.
Interface control register .............................................................................................................................. 21
5.
GPIO............................................................................................................................................................................ 22
6.
Timer 0 and Timer 1 .................................................................................................................................................... 23
6.1.
Timer/counter mode control register (TMOD) .............................................................................................. 23
6.2.
Timer/counter control register (TCON) ........................................................................................................ 24
6.3.
T0、T1 signal swapping............................................................................................................................... 24
7.
Serial interface ............................................................................................................................................................ 25
7.1.
Mode 0 ......................................................................................................................................................... 26
7.2.
Mode 1 ......................................................................................................................................................... 26
7.3.
Mode 2 ......................................................................................................................................................... 27
7.4.
Mode 3 ......................................................................................................................................................... 27
7.5.
Multiprocessor communication .................................................................................................................... 27
7.6.
Baud rate generator ..................................................................................................................................... 28
8.
Watchdog timer ........................................................................................................................................................... 29
9.
Interrupt ....................................................................................................................................................................... 32
10.
Power Management Unit............................................................................................................................................. 37
10.1.
Idle mode ..................................................................................................................................................... 37
10.2.
Stop mode .................................................................................................................................................... 37
11.
PWM - Pulse Width Modulation .................................................................................................................................. 38
12.
IIC function .................................................................................................................................................................. 41
Specifications subject to change without notice contact your sales representatives for the most recent information.
Table of Contents
- 1 -
SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Ver.A SM39R08A5 02/2013
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Table of Contents
Summary of Contents for SyncMOS Technologies International SM39R08A5
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Page 1: Table Of Contents
Stop mode ..............................37 PWM - Pulse Width Modulation ..........................38 IIC function .................................. 41 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 1 -... - Page 2 DC Characteristics ................................53 ADC Characteristics ................................55 Comparator Characteristics ............................... 55 LVI& LVR Characteristics..............................56 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 2 -...
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Page 3: Product List
Instruction-set compatible with MCS-51. 22.1184MHz Internal RC oscillator, with Description programmable clock divider The SM39R08A5 is a 1T (one machine cycle per clock) 8K Bytes on-chip flash program memory. single-chip 8-bit microcontroller. It has 8K-byte 256 bytes RAM as standard 8052, embedded Flash for program, and executes all ASM51 ... -
Page 4: Pin Configuration
1. The pin Reset/P3.6 factory default is GPIO(P3.6). User can configure it to Reset by a flash programmer. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 4 -... -
Page 5: Block Diagram
RESET UART comparator SRAM 256Bytes Port 3 Port 3 INT0/1 Flash 8KBytes Watchdog Interrupt Timer 0/1 Interface control Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 5 -... -
Page 6: Pin Description
- External interrupt 1 - Cmp0Out - Comparator 0 output - ADC7 - ADC input channel 7 Power supply Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 6 -... -
Page 7: Special Function Register (Sfr)
IEN2 IRCON2 TCON TMOD CKCON IFCON DPL1 DPH1 PCON Note: Special Function Registers reset values and description for SM39R08A5 Register Location Reset value Description Stack Pointer Data Pointer 0 low byte Data Pointer 0 high byte DPL1 Data Pointer 1 low byte... - Page 8 ISP Flash control register Low voltage control register SWRES Software Reset register B Register OPPIN Op/Cmp pin select Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 8 -...
- Page 9 IIC channel Address 2 register IICRWD IIC channel Read / Write Data buffer IICEBT IIC Enable Bus Transaction CMP0CON Comparator 0 control Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 9 -...
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Page 10: Function Description
& 256B RAM embedded Function Description 1. General Features SM39R08A5 is an 8-bit micro-controller. All of its functions and the detailed meanings of SFR will be given in the following sections. 1.1. Embedded Flash The program can be loaded into the embedded 8KB Flash memory via its writer. The high-quality Flash has a 100K-write cycle life, suitable for re-programming and data recording as EEPROM. -
Page 11: Reset
1.5.2. Software RESET function SM39R08A5 provides one software reset mechanism to reset whole chip. To perform a software reset, the firmware must write three specific values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the Software Reset register (SWRES) write attribute. -
Page 12: Time Access Key Register (Takey)
22.1184MHz from internal OSC 11.0592MHz from internal OSC 5.5296MHz from internal OSC 2.7648MHz from internal OSC 1.3824MHz from internal OSC Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 12 -... -
Page 13: Instruction Set
& 256B RAM embedded 2. Instruction Set All SM39R08A5 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. The following tables give a summary of the instruction set cycles of the SM39R08A5 Microcontroller core. - Page 14 RR A Rotate accumulator right RRC A Rotate accumulator right through carry SWAP A Swap nibbles within the accumulator Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 14 -...
- Page 15 XCH A,@Ri Exchange indirect RAM with accumulator C6-C7 XCHD A,@Ri Exchange low-order nibble indir. RAM with A D6-D7 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 15 -...
- Page 16 OR complement of direct bit to carry MOV C,bit Move direct bit to carry flag MOV bit,C Move carry flag to direct bit Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 16 -...
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Page 17: Memory Structure
3.1. Program Memory The SM39R08A5 has 8KB on-chip flash memory which can be used as general program memory or EEPROM. The address range for the 8K byte is $0000 to $1FFF. It can be used to record any data as EEPROM. The procedure of this EEPROM application function is described in the section 15. -
Page 18: Data Memory
8KB Flash & 256B RAM embedded 3.2. Data Memory The SM39R08A5 has 256Bytes on-chip SRAM; 256 Bytes of it are the same as general 8052 internal memory structure Higher 128 Bytes (Accessed by SFR (Accessed by direct addressing indirect addressing mode only) -
Page 19: Cpu Engine
Arithmetic – logic unit c. Memory control unit d. RAM and SFR control unit The SM39R08A5 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The following chapter describes the main engine register. Mnemonic... -
Page 20: Program Status Word
DPL[7:0]: Data pointer Low 0 Mnemonic: DPH Address: 83h Reset DPH [7:0] DPH [7:0]: Data pointer High 0 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 20 -... -
Page 21: Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the SM39R08A5 core the standard data pointer is called DPTR; the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located in LSB of AUX register (DPS). -
Page 22: Gpio
Two configuration registers for each port select the output type for each port pin. All I/O port pins on the SM39R08A5 may be configured by software to one of four types on a pin-by-pin basis, shown as below:... -
Page 23: Timer 0 And Timer 1
& 256B RAM embedded 6. Timer 0 and Timer 1 The SM39R08A5 has two 16-bit timer/counter registers: Timer 0 and Timer 1. All can be configured for counter or timer operations. In timer mode, the Timer 0 register or Timer 1 register is incremented every 12 machine cycles, which means that it counts up after every 12 periods of the clock signal. -
Page 24: Timer/Counter Control Register (Tcon)
Mnemonic: AUX Address: 91h Reset BRGS PTS [1:0] PINTS[1:0] PTS [1:0] 0x00 0x01 P3.3(PA03) P3.2(PA02) 0x10 P3.0(PA00) P3.1(PA01) 0x11 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 24 -... -
Page 25: Serial Interface
RI: Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 25 -... -
Page 26: Mode 0
1 can be use to specify baud rate. Fig. 7-3: Transmit mode 1 Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 26 -... -
Page 27: Mode 2
9 bit set to 0, so no serial port receive interrupt will be generated in unselected slaves. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 27 -... -
Page 28: Baud Rate Generator
(b) When BRGS = 1 (in SFR AUX): SMOD Baud Rate SREL Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 28 -... -
Page 29: Watchdog Timer
Watch Dog Timer refresh Key (WDTK) register. This will clear the content of the 8-bit counter and let the counter re-start Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 29 -... - Page 30 When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by software. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 30 -...
- Page 31 ; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT ; function. MOV WDTK, #55h ; Clear WDT timer to 0. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 31 -...
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Page 32: Interrupt
& 256B RAM embedded 9. Interrupt The SM39R08A5 provides 9 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled by the enable bits in SFR’s IEN0, and IEN1. - Page 33 ET0=1 – Enable Timer 0 overflow interrupt. EX0: EX0=0 – Disable external interrupt 0. EX0=1 – Enable external interrupt 0. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 33 -...
- Page 34 HW will clear this flag automatically when enter interrupt vector. SW can clear this flag also.(in case analog comparator INT disable) WDTIF: WDT interrupt flag. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 34 -...
- Page 35 ADC interrupt IP1.3, IP0.3 Timer 1 interrupt IP1.4, IP0.4 Serial channel interrupt LVI interrupt IP1.5, IP0.5 IIC interrupt Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 35 -...
- Page 36 External interrupt 1 Comparator interrupt ADC interrupt Timer 1 interrupt Serial channel 0 interrupt LVI interrupt IIC interrupt Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 36 -...
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Page 37: Power Management Unit
INT0/1, LVI and WDT interrupt, or hardware reset by WDT and LVR. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 37 -... -
Page 38: Pwm - Pulse Width Modulation
SM39R08A5 8-Bit Micro-controller with 8KB Flash & 256B RAM embedded 11. PWM - Pulse Width Modulation SM39R08A5 provides four-channel PWM outputs. The interrupt vector is 43h. Mnemonic Description Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2... - Page 39 “1” – PWM channel 2 will idle high. PWMD2[9:0]: PWM channel 2 data register. Mnemonic: PWMD3H Address: B3h Reset Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 39 -...
- Page 40 PWMPx = 1 & PWMDx = 00h PWMPx = 1 & PWMDx ≠ 00h PWMMD period clock PWMDx Leader pulse clock Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 40 -...
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Page 41: Iic Function
MStart is set. Set this bit when multi-master and slave connection. Clear this bit when single master to single slave. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 41 -... - Page 42 IIC bus (SDA).(Slave mode only) Fig. 11-1: Acknowledgement bit in the 9 bit of a byte transmission Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 42 -...
- Page 43 If it is 1, the module is in master receive mode. If 0, the module is in master transmit mode. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 43 -...
- Page 44 IICRWD before setting FU_EN[7:6] as 01. 4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6] repeatedly is necessary. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 44 -...
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Page 45: Lvi - Low Voltage Interrupt
LVIS[1:0] = 01 VIL=2.47V VIL=2.60V VIL=2.73V LVIS[1:0] = 10 VIL=3.04V VIL=3.20V VIL=3.36V LVIS[1:0] = 11 VIL=3.80V VIL=4.00V VIL=4.20V Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 45 -... -
Page 46: Bit Analog-To-Digital Converter (Adc)
8KB Flash & 256B RAM embedded 14. 10-bit Analog-to-Digital Converter (ADC) The SM39R08A5 provides eight channels 10-bit ADC. The Digital output DATA [9:0] were put into ADCD [9:0]. The ADC interrupt vector is 53H. The ADC SFR show as below:... - Page 47 ADCD[9] ADCD[8] Mnemonic: ADCDL Address: AEh Reset ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] ADCD[9:0]: ADC data register. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 47 -...
- Page 48 11110 Fosc /62 1426 11111 Fosc /64 1472 Fosc Clock ADCCS ADC_Clock Conversion Rate Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 48 -...
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Page 49: Eeprom
ISPE The bit 0 (ISPE) of IFCON is ISP enable bit. User can enable overall SM39R08A5 EEPROM function by setting ISPE bit to 1, to disable overall EEPROM function by set ISPE to 0. The function of ISPE behaves like a security key. - Page 50 The choice EEPROM function will start to execute once the software write data to ISPFC register. To perform byte program/page erases function, user need to specify flash address at first. When performing page erase function, SM39R08A5 will erase entire page which flash address indicated by ISPFAH & ISPFAL registers located within the page.
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Page 51: Comparator
& 256B RAM embedded 16. Comparator SM39R08A5 had integrated a Comparator in chip. This module supports Comparator modes individually according to user’s configuration. When use it as comparator, the comparator output is logical one when positive input greater than negative input, otherwise the output is a zero. - Page 52 Cmp0OutEN: Comparator_0 Output Enable 0: Comparator_0 will not output to external Pin 1: Comparator_0 will output to external Pin Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 52 -...
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Page 53: Dc Characteristics
Power down mode V =5V 25 ℃ Notes： 1. Port in Push-Pull Output Mode 2. Port in Quasi-Bidirectional Mode Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 53 -... - Page 54 Absolute Maximum Ratings SYMBOL PARAMETER UNIT Maximum sourced current Total I/O pins (Push-pull) Maximum sunk current Total I/O pins Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 54 -...
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Page 55: Adc Characteristics
Condition Operating current Power Down Current Offset voltage Input voltage commom mode Vdd-1.5 range △ Propagation delay Vin=10mV Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 55 -... -
Page 56: Lvi& Lvr Characteristics
Low Voltage Interrupt Voltage Level Low Voltage Reset Voltage Level Notes : The V always above V about 0.2V. Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M067 Ver.A SM39R08A5 02/2013 - 56 -...
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