Sony STR-DE845 Training Manual page 18

Circuit Description
Data, Clock, and Chip Enable Lines
The control lines for IC1401 (IC1201/parallel data lines 17 to 24, pin 25 (address line) and pin 16 (CE)) and
IC1503 (IC1201/pins 30 (data), 29 (CLK) and 28 (CE)) are only present during input switching. The waveforms
on the control lines are the same as those shown in Waveforms 4-1, 4-2 and 4-3, except standby voltage state
is high (5V dc).
The waveforms on the control lines for IC1101 (IC1201/pins 112 (data), 110 (CLK), and 111 (CE)), and IC1301
(IC1201/pins 1 (CLK), 2 (data), and 3 (CE)) are always present as digital data is present at one of the digital input
jacks (optical or coax). Waveforms 4-4 and 4-5 illustrate what is displayed on the oscilloscope. When the Input
mode is set to Analog input, all three control lines on IC1101 are inactive and the chip select line on IC1301 is
inactive (the other two lines on IC1301 are active with data, but the chip is not enabled).
The following waveforms can be viewed on the oscilloscope continuously when digital data is present at the
digital inputs and that digital input is selected.
Oscilloscope Settings:
5V/div.
100us/div or 50us/div
Trigger rising edge
DATA
CLK
CE
WAVEFORM 4-4
Master, Bit and Left/Right Channel Clock lines
All the control lines discussed so far are used either for input/output switching or to set up an IC for a particular
function (e.g. Dolby Digital decoding). The Clock lines that will be looked at now are used for data manipulation.
The Clock lines MCLK (Master Clock), BCLK (Bit Clock) and LRCLK (Left Right channel Clock) are all developed
by IC1101 using X3501 (12.282MHz). The MCLK is applied only to IC1503 (CODEC), while BCLK and LRCLK
are applied to IC1301 and IC1503. These Clock lines are used to synchronize the system to the incoming audio
data stream so that appropriate decoding and coding can be performed. The following waveforms are always
present and can be viewed easily with the oscilloscope. Waveform 4-7 is an expanded view of Waveform 4-6.
The frequency for each clock signal is as follows:
MCLK —— 12.282MHz
BCLK —— 3MHz
LRCLK — 48KHz
Oscilloscope Settings:
5V/div.
2us and 200ns/div
Trigger rising edge
Data and Control Line Waveforms for IC1101
MCLK
BCLK
LRCK
WAVEFORM 4-6
DATA
CLK
CE
MCLK
BCLK
LRCK
16
4. Control Signal Block
WAVEFORM 4-5
WAVEFORM 4-7