Pentek 71620 Manuals

Manuals and User Guides for Pentek 71620. We have 1 Pentek 71620 manual available for free PDF download: Operating Manual

Pentek 71620 Operating Manual

Pentek 71620 Operating Manual (258 pages)

3-Channel 200 MHz A/D, 2-Channel 800 MHz D/A Cobalt Family XMC Module

Brand: Pentek | Category: Control Unit | Size: 1.26 MB

Table of Contents
4
Chapter 1: Introduction

18
- General Description
  18
- Features
  18
- Block Diagram
  19
- Principle of Operation
  20
- Analog to Digital Input Conversion
  21
- Digital to Analog Output Conversion
  21
- FPGA Digital Interfaces
  21
- FPGA Configurations
  21
- Memory
  22
- Timing and Synchronization
  22
- XMC Baseboard Interfaces
  22
- Board Support Software
  23
- Supporting Documentation
  23
- Specifications
  24
Chapter 2: Installation and Connections

30
- Inspection
  30
- DIP Switch Settings
  31
- PCB Jumpers
  35
- PCB Leds
  36
- Baseboard Connectors
  37
- Installing the Model 71620 on an XMC Baseboard
  39
- Figure 2−7: Baseboard PMC/XMC Connections
  40
- Front Panel Connections
  41
  - Clock Input Connector
    41
  - Analog Output Connectors
    42
  - Analog Input Connectors
    42
  - Sync Bus Connector
    43
- Front Panel Leds
  44
  - Link LED
    44
  - User LED
    44
  - Master LED
    44
  - Pps Led
    44
  - Over Temperature LED
    44
  - Clock LED
    44
  - DAC Underrun LED
    44
  - ADC Overload Leds
    44
Chapter 3: Model 71620 Resource Operation

46
- Overview
  46
- Analog to Digital Input
  47
  - ADC Data Packing Formats
    48
    
    Real−Only Packed
    49
    
    Real−Only Unpacked
    49
    
    I/Q Packed
    50
    
    I/Q Unpacked
    50
  - ADC Input Linked List Operation
    51
  - Table 3−6: ADC1 Trigger Controller Linked List RAM
    53
  - Table 3−7: ADC1 Trigger Controller Linked List RAM
    54
  - ADC DMA Operation
    55
  - ADC DMA Linked Lists
    58
  - Table 3−10: ADC Link Control Word Format
    59
- Digital to Analog Output
  61
- RAM Memory Operation
  74
- Timing and Synchronization
  75
  - Gates
    75
  - Figure 3−5: Gate Logic Diagram
    76
  - Syncs
    77
  - Clocks
    78
- Interrupt Operation
  79
  - Pcie Interrupts
    80
  - Global Interrupts
    81
  - ADC Interrupts
    82
  - DAC Interrupts
    83
- FPGA Resources Operation
  84
- FLASH Memory Operation
  88
- User Register Address Space
  88
Chapter 4: Model 71620 Memory Maps

90
- Overview
  90
- Default FPGA Memory Map
  91
Chapter 5: Global Registers

98
- Overview
  98
- Link Status Register
  99
  - Msi Enabled
    100
  - Max Rd Rqst
    100
  - Max Payload
    100
  - Sel Link Width
    101
  - Core Nom Width
    101
  - Sel Link Rate
    101
  - Core Nom Speed
    101
  - Link Upcfg Cap
    101
  - Partner Gen2 Sprt
    101
  - Link Gen2 Cap
    102
  - Lane Rvrsl Mode
    102
  - Initial Link Width
    102
- Interrupt Flag Register
  103
- Interrupt Enable Register
  105
- Byte Swap Register
  106
- Interrupt Control Register
  107
- Global Register Reset Register
  108
- Board Identification Register
  109
- Daughter Board ID Register
  110
  - Fpga Type
    110
  - Fpio Type
    110
  - Mem CD Type
    111
  - Mem Ab Type
    111
- FPGA Code Type Register
  112
  - Fpga Code Expl
    112
  - Mem CD Code
    112
  - Mem Ab Code
    113
  - Fpga Code ID
    113
  - Code Type
    113
- FPGA Code Revision Register
  114
- FPGA Date Code Register
  115
- ICAP Register
  116
- CDC Control/Status Register
  117
  - Busy
    117
  - Prgm
    118
  - Reset
    118
  - Rst en
    119
  - Vcxo Stat
    119
  - Ref Stat
    119
  - Lock
    119
- CDC Data Register
  120
  - CDC Word 0 Register
    121
  - CDC Word 1 Register
    122
  - CDC Word 2 Register
    123
- Clock Control/Status Register
  124
  - CDC Rdy
    124
  - CDC Clkb/Clka Locked
    124
  - CDC Clkb/Clka Det
    125
  - Fpga Clkb/Clka Src Sel
    125
  - Fpga Clkb/Clka Pwr Dwn
    125
- Sync Bus Control Register 1
  126
  - Sbus Syncb Drv Inv
    127
  - Sbus Gateb Drv Inv
    127
  - Sbus Synca Drv Inv
    127
  - Sbus Gatea Drv Inv
    127
- Sync Bus Control Register 1 (Continued)
  127
  - Sbus Syncb Drv Src
    127
  - Sbus Gateb Drv Src
    127
  - Sbus Synca Drv Src
    127
  - Sbus Gatea Drv Src
    128
  - Clk Sel
    128
  - Vcxo out Disable
    128
  - Gateb/Syncb Mstr
    128
  - Gatea/Synca Mstr
    129
  - Clk Master en
    129
- Sync Bus Control Register 2
  130
  - Pps/Sync/Gate A/B Edge
    130
  - Pps/Sync/Gate A/B Pol
    131
  - Pps B Rcv Src
    131
  - Sync B Rcv Src
    131
  - Gate B Rcv Src
    131
  - Pps a Rcv Src
    132
  - Sync a Rcv Src
    132
  - Gate a Rcv Src
    132
- Sync Bus Input Delay Tap Control Register
  133
  - Iodelay Cntrl Rdy
    133
  - Sbus Sync B/A in Dly
    134
  - Sbus Gate B/A in Dly
    134
- Sync Bus Input Delay Control Register
  135
  - Sbus Sync B/A in Dly
    135
  - Sbus Gate B/A in Dly
    135
- User LED Register
  136
- LED Control Register
  137
  - Clk Det Led Ctrl
    137
  - Almn/Ot LED DISABLE
    138
  - Pps Led Src
    138
  - Pps Led Disable
    138
  - User Led Src
    138
  - XXX MSTR LED DISABLE
    139
- Gate a Generate Register
  140
- Gate B Generate Register
  140
- Sync a Generate Register
  141
- Sync B Generate Register
  142
- Test Signal and Timestamp Control Register
  143
  - Ts Start Time Load
    143
  - Ts Pps Sig en
    143
  - Ts Synca Rst en
    144
  - Ts Module Rst
    144
  - Sys Mon Rst
    144
  - Test Sig Syncb Rst en
    144
  - Test Sig Synca Rst en
    144
  - Test Sig Rst
    144
- Test Sine a Frequency Control Register
  145
- Test Sine B Frequency Control Register
  145
- Timestamp Start Time Register
  146
- TWSI Port 1 Control/Status Register
  147
  - Rx Fifo Cnt[4:0]
    148
  - Rx Fifo Full
    148
  - Rx Fifo Empty
    148
  - Tx Fifo Full
    148
  - Tx Fifo Empty
    148
  - Trnsfr Busy
    148
  - Twsi Addr[6:0]
    149
  - Start Trnsfr
    149
  - Data dir
    149
  - Port Enable
    149
  - Num Bytes[3:0]
    149
- TWSI Port 1 Data Register
  151
- TWSI Port 2 Control/Status Register
  154
  - Mga[2:0]
    155
  - Rx Fifo Cnt[4:0]
    155
  - Rx Fifo Full
    155
  - Rx Fifo Empty
    155
  - Tx Fifo Full
    155
  - Tx Fifo Empty
    155
  - Trnsfr Busy
    155
  - Twsi Addr[6:0]
    156
  - Start Trnsfr
    156
  - Data dir
    156
  - Port Enable
    156
  - Num Bytes[3:0]
    156
- TWSI Port 2 Data Register
  158
- Global Interrupt Enable Register
  162
Chapter 6: Analog to Digital Channel Registers

166
- Overview
  166
- Channel Status/Power Management Registers
  167
  - Dma Dsbl
    167
  - MMCM Pwr Dwn
    167
  - Mem Ctrl Dsbl
    168
  - Adc Pwr Dn
    168
  - Acq Type
    168
  - Chan Present
    168
- ADC Input Delay Tap Control Registers
  169
- ADC Data Control Registers
  170
  - Sync Sel
    170
  - Ov Led Sel
    171
  - Ts Sub en
    171
  - Adc Dither
    171
  - Pack Fifo Rst
    171
  - Usr Dat Sel
    171
  - Pack Mode
    171
  - Data Src
    172
- ADC Rate Divider Registers
  173
- ADC Gate/Trigger Control Registers
  174
  - Loc Gate Sel
    174
  - Trig Linked List Rst
    175
  - Timestamp Fifo Rst
    175
  - Trig Num Rst
    175
  - Pps Latch en
    175
  - Usr Dval en
    175
  - Trig Clr
    176
  - Trig Hold
    176
  - Gate Trig in en
    176
  - Trig Mode
    176
- ADC Trigger Gen Linked List Start Pointer Registers
  177
- Local Gate Generate Registers
  178
- RAM Control Registers
  179
  - Ram Read en
    179
  - Ram Path en
    179
  - Ram Rst
    180
  - Mem Ctlr Rst
    180
- Input DC Offset Registers
  181
- Input Gain Trim Registers
  182
- ADC DMA Control Registers
  183
  - Byte Swap
    183
  - Dma at
    184
  - Dma Tc
    184
- ADC DMA Control Registers (Continued)
  184
  - Dma Attr1
    184
  - Dma Attr0
    184
  - Dma Abort
    184
  - Dma in Fifo Rst
    185
  - Dma Rst
    185
  - Dma Adv
    185
- ADC Interrupt Enable Registers
  186
- Table 6−13: ADC Interrupt Register Bits
  
  187
- ADC Interrupt Flag Registers
  188
- ADC Interrupt Status Registers
  189
- Idelay and Clock Status Registers
  190
  - Mem Clk Fb Stopped
    190
  - Mem Clk in Stopped
    190
  - Mem MMCM Lock
    190
  - Mem Iodly Ctrl Rdy
    191
  - Fpga Clka Not Det
    191
  - CDC Clka Lock
    191
  - Adc Iodly Ctrl Rdy
    191
- RAM Controller Status Registers
  192
  - Ram Fifo Full
    192
  - Ram Fifo Afl
    192
  - Ram Fifo Aem
    193
  - Ram Fifo Emp
    193
  - Ddr Det
    193
  - Ddr Phy Init Done
    193
  - Qdr Det
    193
  - Qdr Cal Cmplt
    193
- RAM FIFO Count Registers
  194
- ADC DMA Status Registers
  195
  - Waiting for Adv
    195
  - Abort in Progress
    195
  - Next Link
    195
- Data Rate Detection Control Registers
  196
  - Data Rate Sync Rst en
    196
  - Data Rate Rst
    196
  - Clr Data Rate Peak
    196
  - Mon Clk Period
    197
- Data Rate Detection Value Registers
  198
- Peak Data Rate Detection Value Registers
  199
Chapter 7: Digital to Analog Channel Registers

200
- Overview
  200
- Channel Status/Power Management Register
  201
  - Dma Dsbl
    201
  - MMCM Pwr Dwn
    201
  - Mem Ctrl Dsbl
    202
  - Acq Type
    202
  - Chan Present
    202
- Output Delay Tap Control Register
  203
- DAC Data Control Register
  204
  - Sync Sel
    204
  - Ur Led en
    204
  - Sync out en
    205
  - Dac Rst
    205
  - Out Fifo Rst
    205
  - Data Src
    205
- DAC Rate Divider Register
  206
- DAC Gate/Trigger Control Register
  207
  - Out Cntrl Linked List Rst
    207
  - Trig Clr
    208
  - Trig Hold
    208
  - Gate Trig in en
    208
  - Trig Mode
    208
- Output Controller Linked List Start Pointer Register
  209
- RAM Capture Start Address Register
  210
- RAM Control Register
  211
  - Ram Capt Addr Ld
    211
  - Ddr3 Data dir
    211
  - Ram Read en
    211
  - Ram Path en
    212
  - Ram Rst
    212
  - Data Repack Rst
    212
  - Mem Ctlr Rst
    212
- Output Gate Delay Register
  213
- DAC DMA Control Register
  214
  - Byte Swap
    214
  - Dma at
    215
  - Dma Tc
    215
  - Dma Attr1
    215
  - Dma Attr0
    215
  - Dma Abort
    215
  - Dma Rst
    216
  - Dma Adv
    216
- DAC Interrupt Enable Register
  217
  - Table 7−12: DAC Interrupt Register Bits
    
    218
  - Table 7−20: DAC5688 Register Addresses
    
    229
  - DAC Serial Data Register
    230
  - Data Rate Detection Control Register
    231
    
    Data Rate Sync Rst en
    231
    
    Data Rate Rst
    231
    
    Clr Data Rate Peak
    231
    
    Mon Clk Period
    231
  - Data Rate Detection Value Register
    232
  - Peak Data Rate Detection Value Register
    233
- DAC Interrupt Flag Register
  219
- DAC Interrupt Status Register
  220
- Odelay and Clock Status Register
  221
  - Mem Clk Fb Stop
    221
  - Mem Clk in Stop
    221
  - Mem MMCM Lock
    221
  - Mem Iodly Ctrl Rdy
    222
  - Fpga Clkb Not Det
    222
  - CDC Clkb Lock
    222
  - Dac Iodly Ctrl Rdy
    222
- RAM Controller Status Register
  223
  - Repack Not Emp
    223
  - Ddr Det
    223
  - Ddr Phy Init Done
    224
  - Qdr Det
    224
  - Qdr Cal Cmplt
    224
- RAM Capture Count Register
  225
- DAC DMA Status Register
  226
  - Waiting for Adv
    226
  - Abort in Progress
    226
  - All Data Rcvd
    227
  - Next Link
    227
- DAC Serial Address Register
  228
  - Serial Busy
    228
  - Ser Addr[4:0]
    228
Appendix A: PCI Configuration Space Registers

235
Table A−2: PCI Base Address Registers

235
- Introduction
  236
- Using Triggered Acquisition of ADC Data
  237
  - Scenario 2
    238
- Using the ADC DMA Engine
  239
Appendix B: Sample 71620 Applications

240
- Scenario 1
  240
- Scenario 1
  248

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Pentek 71620 Manuals

Pentek 71620 Operating Manual (258 pages)

Table of Contents

Chapter 1: Introduction

Chapter 2: Installation and Connections

Chapter 3: Model 71620 Resource Operation

Chapter 4: Model 71620 Memory Maps

Chapter 5: Global Registers

Table 5−3: Interrupt Register Bits

Table 5−44: Global Interrupt Register Bits

Chapter 6: Analog to Digital Channel Registers

Table 6−13: ADC Interrupt Register Bits

Chapter 7: Digital to Analog Channel Registers

Table 7−12: DAC Interrupt Register Bits

Table 7−20: DAC5688 Register Addresses

Appendix A: PCI Configuration Space Registers

Table A−2: PCI Base Address Registers

Appendix B: Sample 71620 Applications

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