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Pentek 71620 Operating Manual

3-channel 200 mhz a/d, 2-channel 800 mhz d/a cobalt family xmc module
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  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 Pentek Model 71620 Operating Manual Page 1 OPERATING MANUAL MODEL 71620 3−Channel 200 MHz A/D, 2−Channel 800 MHz D/A Cobalt Family XMC Module Pentek, Inc. One Park Way Upper Saddle River, NJ 07458 (201) 818−5900 http://www.pentek.com Copyright © 2010−2017 Manual Part No: 800.71620 Rev: 2.14 −...
  • Page 3 The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product that in Pentek’s sole opinion proves to be defective within the scope of the warranty.

  • Page 4: Table Of Contents

    1.14 Specifications............................23 Chapter 2: Installation and Connections Inspection.............................29 Figure 2−1: Model 71620 PCB Assembly Drawing, Connector Side ........29 DIP Switch Settings ..........................30 Figure 2−2: Model 71620 Main PCB Assembly Drawing, Solder Side........30 2.2.1 Switch SW1 − FPGA MGT Clock Operation ..............31 Table 2−1: SW1 −...
  • Page 5 Pentek Model 71620 Operating Manual Table of Contents Page Chapter 2: Installation and Connections (continued) Front Panel Connections ........................40 Figure 2−8: Model 71620 Front Panel.................... 40 2.7.1 Clock Input Connector ....................40 2.7.2 Analog Output Connectors ..................... 41 2.7.3 Analog Input Connectors ....................
  • Page 6 Pentek Model 71620 Operating Manual Page 5 Table of Contents Page Chapter 3: Model 71620 Resource Operation (continued) Digital To Analog Output .........................60 Figure 3−3: Digital to Analog Output Data Flow ................60 3.3.1 DAC DMA Linked Lists ....................61 Table 3−11: DAC DMA Linked List RAM..............61 Table 3−12: DAC Link Control Word Format .............62...
  • Page 7 Table of Contents Page Chapter 4: Model 71620 Memory Maps Overview ............................. 89 Table 4−1: Model 71620 PCI Memory Map .................. 89 Default FPGA Memory Map ......................90 Table 4−2: Default FPGA Memory Map..................90 Chapter 5: Global Registers Overview ............................. 97 Link Status Register ...........................
  • Page 8 Pentek Model 71620 Operating Manual Page 7 Table of Contents Page Chapter 5: Global Registers (continued) 5.10 FPGA Code Type Register.......................111 Table 5−10: FPGA Code Type Register ..................111 5.10.1 FPGA CODE EXPL ......................111 5.10.2 MEM CD CODE ......................111 5.10.3 MEM AB CODE ......................112 5.10.4...
  • Page 9 Page 8 Pentek Model 71620 Operating Manual Table of Contents Page Chapter 5: Global Registers (continued) 5.17 Sync Bus Control Register 1 (continued) 5.17.5 SBUS SYNCB DRV SRC ....................126 5.17.6 SBUS GATEB DRV SRC ....................126 5.17.7 SBUS SYNCA DRV SRC ....................126 5.17.8...
  • Page 10 Pentek Model 71620 Operating Manual Page 9 Table of Contents Page Chapter 5: Global Registers (continued) 5.25 Sync A Generate Register ........................140 Table 5−28: Sync A Generate Register..................140 5.26 Sync B Generate Register.........................141 Table 5−29: Sync B Generate Register ..................141 5.27...
  • Page 11 Page 10 Pentek Model 71620 Operating Manual Table of Contents Page Chapter 5: Global Registers (continued) 5.33 TWSI Port 2 Control/Status Register .................... 153 Table 5−39: TWSI Port 2 Control/Status Register ..............153 5.33.1 MGA[2:0] ......................... 154 5.33.2 RX FIFO CNT[4:0] ......................154 5.33.3...
  • Page 12 Pen tek Model 7 16 20 O p erating Manual Page 11 Table of Contents Page Chapter 6: Analog to Digital Channel Registers (continued) ADC Data Control Registers ......................169 Table 6−3: ADC Data Control Registers ..................169 6.4.1 SYNC SEL ........................169 6.4.2 OV LED SEL ........................170 6.4.3...
  • Page 13 Page 12 Pentek Model 71620 Operating Manual Table of Contents Page Chapter 6: Analog to Digital Channel Registers (continued) 6.12 ADC DMA Control Registers (continued) 6.12.4 DMA ATTR1 ........................183 6.12.5 DMA ATTR0 ........................183 6.12.6 DMA ABORT ........................183 6.12.7...
  • Page 14 Pen tek Model 7 16 20 O p erating Manual Page 13 Table of Contents Page Chapter 6: Analog to Digital Channel Registers (continued) 6.20 Data Rate Detection Control Registers ..................195 Table 6−20: Data Rate Detection Control Registers..............195 6.20.1 DATA RATE SYNC RST EN ..................195 6.20.2 DATA RATE RST ......................195 6.20.3...
  • Page 15 Page 14 Pentek Model 71620 Operating Manual Table of Contents Page Chapter 7: Digital to Analog Channel Registers (continued) Output Controller Linked List Start Pointer Register..............208 Table 7−6: Output Controller Linked List Start Pointer Register.......... 208 RAM Capture Start Address Register ................... 209 Table 7−7: RAM Capture Start Address Register ..............
  • Page 16 Pen tek Model 7 16 20 O p erating Manual Page 15 Table of Contents Page Chapter 7: Digital to Analog Channel Registers (continued) 7.16 RAM Controller Status Register .....................222 Table 7−16: RAM Controller Status Register ................222 7.16.1 REPACK NOT EMP .......................222 7.16.2 DDR DET .........................222 7.16.3...
  • Page 17 Page 16 Pentek Model 71620 Operating Manual Table of Contents Page Appendix A: PCI Configuration Space Registers Introduction ............................1 PCI Configuration Space Registers....................1 Table A−1: PCI Configuration Space Header (Type 00h) ............1 Table A−2: PCI Base Address Registers ..................2 Appendix B: Sample 71620 Applications Introduction ............................

  • Page 18: Chapter 1: Introduction

    HF or IF ports of a communications or radar system. It includes three 200−MHz, 16−bit A/D converters and two 800−MHz D/A upconverters. ® The 71620 is compatible with the VITA 42.0 XMC format and supports PCI Express ® (PCIe ) Gen 1 or 2 as a native interface.

  • Page 19: Block Diagram

    Page 18 Pentek Model 71620 Operating Manual Block Diagram The following is a simplified block diagram of the Model 71620 module. IN 1 IN 2 IN 3 OUT 1 OUT 2 RF In RF In RF In RF Out RF Out...

  • Page 20: Principle Of Operation

    Page 19 Principle of Operation The Model 71620 is an A/D module suitable for direct connection to HF or IF ports of a communications or radar system. Using the popular XMC module format, it includes three A/D converters and two D/A converters.

  • Page 21: Analog To Digital Input Conversion

    XC6VLX130T, Option 062 is XC6VLX240T, Option 063 is XC6VLX365T, Option 064 is XC6VSX315T, and Option 065 is XC6VSX475T. The 71620 is shipped with a default set of logic functions for the FPGA, on FLASH memory. The 71620 loads the FPGA configuration from FLASH memory at power−up.

  • Page 22: Memory

    In the slave mode, it accepts LVPECL inputs that drive the clock, sync and gate signals. In the master mode, the LVPECL bus can drive the timing signals for synchronizing multiple modules. Multiple 71620’s can be driven from the LVPECL bus master, supporting synchronous sampling and sync functions across all connected modules.

  • Page 23: Board Support Software

    Pentek’s ReadyFlow Board Support Packages (BSP) contain software support for the Model 71620 XMC. This includes a device driver for the 71620, plus the ReadyFlow Board Support Library data structures and routines. The following available BSPs allow high−level programming for various workstation platforms. Refer to the soft−...

  • Page 24: Specifications

    Pen tek Model 7 16 20 O p erating Manual Page 23 1.14 Specifications Analog Signal Inputs Quantity: Three signal inputs Connector Type: Front panel SSMC connectors, IN 1, IN 2, & IN 3 Input Type: Single−ended, non−inverting Full Scale Input: +8 dBm Transformer coupled Coupling:...
  • Page 25 Bus termination provided by in−line cable end terminator Bus Termination: Nr Boards Supported: Up to four boards can be synchronized with a ribbon cable. Pentek’s Model 7893 Synchronizer PCIe board allows synchronization of up to eight boards. External Clock Input Connector Type:...
  • Page 26 Xilinx Virtex−6 XC6VLX365T Option 064: Xilinx Virtex−6 XC6VSX315T Option 065: Xilinx Virtex−6 XC6VSX475T Configuration: Factory programmed by Pentek: A/D, D/A, RAM Memory, FIFOs RAM memory Memory Module 1 Option 150: 16 MB QDRII+ SRAM, 2 banks of 4M x 16...
  • Page 27 Page 26 Pentek Model 71620 Operating Manual 1.14 Specifications (continued) XMC Interfaces PCI Express Interface XMC Connector: 114−pin (XMC standard Pn5 connector), P15 Compliance: VITA 42.3 XMC PCI Express Protocol Standard Lanes/Speed: Gen1 x8 − 2 GB/sec Gen2 x4 − 2 GB/sec Gen2 x8 −...
  • Page 28 Depth: 149.0 mm (5.87 in) Height: 74 mm (2.91 in) Approximately 14 oz (400 grams), with 2−slot heatsink Weight: Environmental Pentek Ruggedization Level L1 Pentek Option Number: −701 (default) Cooling Method (operational): Forced Air Operating Temperature: 0° to 50° C Storage Temperature: −40°...
  • Page 29 Page 28 Pentek Model 71620 Operating Manual This page is intentionally blank Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 30: Chapter 2: Installation And Connections

    (P16: Option 105) Figure 2−1: Model 71620 PCB Assembly Drawing, Connector Side Note that a heat sink may be mounted on the 71620 PCB assembly as shipped. The Model 71620 is shipped to boot with the Gen 1 x8 PCIe default FPGA Note code.

  • Page 31: Dip Switch Settings

    SW1 and SW2 on the PCB. Switch Switch Figure 2−2: Model 71620 Main PCB Assembly Drawing, Solder Side Note that several user LEDs are located on the solder side of the 71620 PCB. Refer to Section 2.4, on page 35 for description of these LEDs.

  • Page 32: Switch Sw1 − Fpga Mgt Clock Operation

    Note: Primary and Secondary PCIe Clock Frequencies − 100 MHz XMC clock source is converted to 250 MHz in the default position. SW1−1 ** Switch must be in the OFF (250 MHz) position for Pentek factory FPGA code and for any x8 or Gen 2 design. SW1−8 *** Switch , when in the ON position clock source is the Option 105 XMC P16 connector −...

  • Page 33: Figure 2−3: Model 71620 Fpga Mgt Clock Logic

    AUX_MGT_CLK_B Attenuator F_SEL SW1 - 3&4 & Divider AUX_MGT_CLK_C SW1 - 6 Aux MGT Clock Frequency Select Figure 2−3: Model 71620 FPGA MGT Clock Logic Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 34: Switch Sw2 − Fpga Configuration

    Pen tek Model 7 16 20 O p erating Manual Page 33 DIP Switch Settings (continued) 2.2.2 Switch SW2 − FPGA Configuration Switch SW2 controls access to the FPGA configuration functions. The fol− lowing table shows the settings for this switch. Use ballpoint tip only for setting DIP switches.

  • Page 35: Pcb Jumpers

    The following describes user operating parameters that are set by jumper block J28 on the Model 71620 PCB. This jumper block is located on the connector side of the Model 71620 main PCB (Pentek part number 320−71600). An assembly drawing of the con−...

  • Page 36: Pcb Leds

    These LEDs are positioned on the solder side of the Model 71620 main PCB, as illustrated below, and are visible through the heat sink mounted on the PCB. The use of each LED is indicted in Table 2−6...

  • Page 37: Baseboard Connectors

    Page 36 Pentek Model 71620 Operating Manual Baseboard Connectors The following subsections describe the baseboard PMC/XMC connectors on the 71620 PCB. Refer to Figure 2−1 page 29 for the location of these connectors on the PCB. 2.5.1 XMC Connectors The Model 71620 provides an XMC high−speed serial connector, identified as P15, that complies with the VITA 42.3 XMC Standard.

  • Page 38: Pmc Fpga Connections (Option 104)

    (continued) 2.5.2 PMC FPGA Connections (Option 104) Option 104 for the Model 71620 provides connections from FPGA spare pins to the baseboard or carrier using PMC connector P14. These connections are programmed for low−voltage differential signals (LVDS) in the default FPGA configuration;...

  • Page 39: Installing The Model 71620 On An Xmc Baseboard

    Pentek Model 71620 Operating Manual Installing the Model 71620 on an XMC Baseboard The Model 71620 mounts on the connector side of an XMC baseboard or carrier. Refer to the operating manual supplied with your baseboard for any specific mounting instructions.

  • Page 40: Figure 2−7: Baseboard Pmc/Xmc Connections

    4) Position the Model 71620 front panel into the opening from behind the baseboard front panel, and position the module so that the 71620 XMC connectors are over the XMC connectors on the baseboard (see illustration below).

  • Page 41: Front Panel Connections

    Pentek Model 71620 Operating Manual Front Panel Connections The Model 71620 XMC front panel, illustrated in the figure at the right, includes six SSMC coaxial connectors for input/out− put of clock and analog signals, and a 26−pin Sync Bus input/ output connector.

  • Page 42: Analog Output Connectors

    Pen tek Model 7 16 20 O p erating Manual Page 41 Front Panel Connections (continued) 2.7.2 Analog Output Connectors OUT 1, 2 The front panel has two SSMC coaxial connectors for analog signal outputs, labeled OUT 1 and 2, one for each DAC5688 output. The analog output signal is within the range of +4 dBm.

  • Page 43: Sync Bus Connector

    Logic (LVPECL) Sync Bus. When the Model 71620 is a bus Master, these pins output LVPECL Sync Bus signals to other slave units. When the 71620 is a bus Slave, these pins input LVPECL signals from a bus Master. This connector also accepts two Low−Voltage TTL (LVTTL) Gate/ Sync inputs.

  • Page 44: Front Panel Leds

    Section 5.22) to select the signal source for this LED. 2.8.3 Master LED The yellow MAS LED illuminates when this Model 71620 is the Sync Bus Master (see Sync Bus Control Register 1, Section 5.17). When only a single 71620 is used, it must be a Master.
  • Page 45 Page 44 Pentek Model 71620 Operating Manual This page is intentionally blank Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 46: Chapter 3: Model 71620 Resource Operation

    Pen tek Model 7 16 20 O p erating Manual Page 45 Chapter 3: Model 71620 Resource Operation Overview This chapter describes operation of the Model 71620 resources from an XMC baseboard processor. An overall data flow of the 71620 data flow is provided below. OUT 1 OUT 2...

  • Page 47: Analog To Digital Input

    Pentek Model 71620 Operating Manual Analog to Digital Input The Model 71620 accepts three analog RF inputs at +8 dBm full scale into 50 ohms on front panel connectors, labeled IN 1, 2, and 3. Each of the three inputs is transformer coupled, digitized by a Texas Instruments ADS5485 200−MHz, 16−bit A/D converter...

  • Page 48: Adc Data Packing Formats

    PACK FIFO. (The User Block can be configured with one of a variety of IP cores for custom signal processing, such as Digital Down−Converters; contact Pentek for further information on these IP cores.) Use the associated ADC Data Control Register, Section 6.4,...

  • Page 49: Real−Only Packed

    Page 48 Pentek Model 71620 Operating Manual Analog to Digital Input (continued) 3.2.1 ADC Data Packing Formats (continued) 3.2.1.1 Real−only Packed When PACK MODE is cleared to 00, data is packed with four consecutive real (I) data samples in each 64−bit FIFO word.

  • Page 50: I/Q Packed

    Pen tek Model 7 16 20 O p erating Manual Page 49 Analog to Digital Input (continued) 3.2.1 ADC Data Packing Formats (continued) 3.2.1.3 I/Q Packed When PACK MODE is set to 10, data is packed with two consec− utive I/Q data samples in each 64−bit FIFO word. •...

  • Page 51: Adc Input Linked List Operation

    Page 50 Pentek Model 71620 Operating Manual Analog to Digital Input (continued) 3.2.2 ADC Input Linked List Operation Each ADC channel has a flexible ADC Trigger Controller Linked List Engine that is capable of generating complex gating to control acquisition of ADC data in response to input triggers.
  • Page 52 Pen tek Model 7 16 20 O p erating Manual Page 51 Analog to Digital Input (continued) 3.2.2 ADC Input Linked List Operation (continued) DELAY[31:0] − This value sets the delay in number of ADC CLOCK cycles that the ADC Trigger Controller Linked List waits before opening the acquisition gate.

  • Page 53: Table 3−6: Adc1 Trigger Controller Linked List Ram

    Requirement: 1) The 71620 receives a trigger from an external source. 2) After the trigger, 71620 must acquire data for 23,000 samples then stop. 3) Repeat at each trigger event. Solution: Set up the linked List RAM table as follows: 6.7) = 0x00...

  • Page 54: Table 3−7: Adc1 Trigger Controller Linked List Ram

    4) Waiting another 512 clocks of delay and acquire another 2048 data samples. 5) After a delay of 1011 clock cycles, 71620 must acquire 4000 more samples and then stop. 6) Repeat at each trigger event. Solution: Set up the linked List RAM table as follows: 6.7) = 0x00...

  • Page 55: Adc Dma Operation

    Page 54 Pentek Model 71620 Operating Manual Analog to Digital Input (continued) 3.2.3 ADC DMA Operation Each ADC channel has its own DMA engine that transfers ADC data packets directly to a PCIe memory address (i.e., XMC baseboard memory). Each ADC DMA engine has a linked list RAM capable of storing up to 512 link descriptors.
  • Page 56 Pen tek Model 7 16 20 O p erating Manual Page 55 Analog to Digital Input (continued) 3.2.3 ADC DMA Operation (continued) The Meta Data includes the following data values: Time Stamp Sample Clock Offset Count * − This is a 32−bit Time Stamp Sample Clock Offset Counter.
  • Page 57 Page 56 Pentek Model 71620 Operating Manual Analog to Digital Input (continued) 3.2.3 ADC DMA Operation (continued) FIFO Overflow Flag (F/O) − When this bit is equal to ‘1’ this indicates that a FIFO overflow has occurred in the data of this DMA transfer. This flags that data was lost and may not be contiguous samples.

  • Page 58: Adc Dma Linked Lists

    Pen tek Model 7 16 20 O p erating Manual Page 57 Analog to Digital Input (continued) 3.2.4 ADC DMA Linked Lists ADC DMA Linked List RAM memory map: Table 3−9: ADC DMA Linked List RAM Address Offset * Link Descriptor Link Descriptor Register +0x00000 Link Control Word...

  • Page 59: Table 3−10: Adc Link Control Word Format

    Page 58 Pentek Model 71620 Operating Manual Analog to Digital Input (continued) 3.2.4 ADC DMA Linked Lists (continued) The following table shows the format of the ADC DMA Link Control Word. The paragraphs following the table describe the bits in this word.
  • Page 60 Pen tek Model 7 16 20 O p erating Manual Page 59 Analog to Digital Input (continued) 3.2.4 ADC DMA Linked Lists (continued) Chain End Mode Bit 26 0 − Normal − Chain ends at Link with END CHAIN bit (31) set 1 −...

  • Page 61: Digital To Analog Output

    Pentek Model 71620 Operating Manual Digital To Analog Output The Model 71620 is designed with a maximum output sample rate of 500 MHz in upconverter mode and 800 MSPS in D/A only mode. One Texas Instruments 16−bit DAC5688 is used to produce an analog output.

  • Page 62: Dac Dma Linked Lists

    Pen tek Model 7 16 20 O p erating Manual Page 61 Digital To Analog Output (continued) 3.3.1 DAC DMA Linked Lists The DAC DMA engine has a linked list RAM capable of storing up to 512 link descriptors. The DMA engine reads data from the PCIe interface and writes it directly to the DAC DMA FIFO, for transfer to the DAC output linked list engine (Section...

  • Page 63: Table 3−12: Dac Link Control Word Format

    Page 62 Pentek Model 71620 Operating Manual Digital To Analog Output (continued) 3.3.1 DAC DMA Linked Lists (continued) The following table shows the format of the DAC DMA Link Control Word. The paragraphs following the table describe the bits in this word.
  • Page 64 Pen tek Model 7 16 20 O p erating Manual Page 63 Digital To Analog Output (continued) 3.3.1 DAC DMA Linked Lists (continued) Start Mode Bit 23 0 − Manual Start − Register Write starts execution 1 − Auto − Start execution immediately NOTE: The first link in a chain requires a register write to start regardless of the setting of this bit.

  • Page 65: Dac Output Linked List Operation

    3.3.2 DAC Output Linked List Operation The 71620 DAC Output Controller Linked List Engine can generate complex output gates in response to input triggers as well as allowing for flexible access to multiple waveforms stored in its waveform storage RAM. This is...
  • Page 66 Pen tek Model 7 16 20 O p erating Manual Page 65 Digital To Analog Output (continued) 3.3.2 DAC Output Linked List Operation (continued) DELAY[31:0] − This value sets the delay in number of DAC CLOCK cycles that the DAC Output Controller Linked List waits before opening the output gate.
  • Page 67 Page 66 Pentek Model 71620 Operating Manual Digital To Analog Output (continued) 3.3.2 DAC Output Linked List Operation (continued) RAM_OFFSET (continued) For QDRII+ SRAM: RAM_OFFSET Data RAM Address Data1[15:0] Data2[15:0] Data3[15:0] Data4[15:0] Data5[15:0] Data6[15:0] Data7[15:0] Data8[15:0] Data9[15:0] For DDR3 SDRAM:...
  • Page 68 Pen tek Model 7 16 20 O p erating Manual Page 67 Digital To Analog Output (continued) 3.3.2 DAC Output Linked List Operation (continued) RAM_LENGTH[31:0] − This value sets the span of RAM addresses that are read from the RAM_OFFSET start address before starting over again at the RAM_OFFSET start address again.

  • Page 69: Table 3−14: Dac Output Controller Linked List Ram

    Example #1: Requirement: 1) The 71620 receives a trigger from an external source. 2) The 71620 has QDRII+ waveform storage RAM installed. 3) After the trigger, 71620 outputs waveform #1. Waveform #1 is 135000 I/Q samples long.

  • Page 70: Table 3−15: Dac Output Controller Linked List Ram

    3) After the trigger, 71620 outputs waveform #1. Waveform #1 is 2048 I/Q samples long. 4) 71620 must output waveform #1 for a total three times with a delay of 512 clocks in between each waveform. 5) After a delay of 1011 clock cycles, 71620 must output waveform #2 and wait for the next trigger event.

  • Page 71: Table 3−16: Qdrii+ Waveform Storage Ram

    Page 70 Pentek Model 71620 Operating Manual Digital To Analog Output (continued) 3.3.2 DAC Output Linked List Operation (continued) Example #2 (continued) Table 3−15: DAC Output Controller Linked List RAM (continued) BAR0+0x30840 0x000003F0 DELAY[31:0] = BAR0+0x30844 0x00000F9F LENGTH[31:0] = BAR0+0x30848...

  • Page 72: Dac Data Routing And Formats

    1.13) for description of these input bus modes. The following subsections describe the DAC FIFO data formats used for the Dual Bus and Half Rate Bus modes (Interleaved Bus mode is not recommended on the 71620). 3.3.3.1 Dual Bus Mode − Channel−Packed FIFO When the DAC5688 is set up for Dual Bus mode, each 32−bit...

  • Page 73: Half Rate Bus Mode − Time−Packed Fifo

    Page 72 Pentek Model 71620 Operating Manual Digital To Analog Output (continued) 3.3.3 DAC Data Routing and Formats (continued) 3.3.3.2 Half Rate Bus Mode − Time−Packed FIFO When the DAC5688 is set up for Half Rate Bus mode, each 32−bit FIFO data word contains two consecutive 16−bit samples for...

  • Page 74: Ram Memory Operation

    RAM Memory Operation Two or four independent banks of QDRII+ (Quad Data Rate II+) SRAM or DDR3 (Dou− ble Data Rate 3) SDRAM are available to the Model 71620 FPGA, depending on the Memory Option ordered. The following memory options are available: Memory Module 1 −...

  • Page 75: Timing And Synchronization

    Gate/Sync inputs. The front panel has a coaxial SSMC receptacle for input of an exter− nal sample clock signal. The front panel interface allows one Model 71620 to act as a Master, driving the clock, sync, and/or gate signals to the Sync Bus using LVPECL (Low−Voltage Positive Emit−...

  • Page 76: Figure 3−5: Gate Logic Diagram

    Pen tek Model 7 16 20 O p erating Manual Page 75 Timing and Synchronization (continued) 3.5.1 Gates (continued) The following diagram illustrates the gate/trigger logic and the controlling FPGA registers. Refer to the following sections for descriptions of the regis− ters and linked lists identified in this diagram.

  • Page 77: Syncs

    (continued) 3.5.2 Syncs The 71620 provides SYNC A, SYNC B, PPS A, and PPS B signals for ADC (Sync A), DAC (Sync B), and user applications. These signals can be driven from the front panel Sync Bus LVPECL SYNC input (Section 2.7.4), a Sync...

  • Page 78: Clocks

    Pen tek Model 7 16 20 O p erating Manual Page 77 Timing and Synchronization (continued) 3.5.3 Clocks 71620 clocks can be selected from the front panel Sync Bus LVPECL CLK A input (Section 2.7.4), the front panel CLK input (Section 2.7.1), or the onboard Si571 VCXO.

  • Page 79: Interrupt Operation

    Pentek Model 71620 Operating Manual Interrupt Operation The 71620 XMC module can generate INTA interrupts in legacy mode or MSI inter− rupts. Refer to the Operating Manual supplied with your XMC baseboard for descrip− tion of the board’s interrupt response operation.

  • Page 80: Pcie Interrupts

    Pen tek Model 7 16 20 O p erating Manual Page 79 Interrupt Operation (continued) 3.6.1 PCIe Interrupts The Interrupt Flag and Enable Registers (Sections 5.3 and 5.4) contain inter− rupt bits for the board. These Interrupts include the following: •...

  • Page 81: Global Interrupts

    Page 80 Pentek Model 71620 Operating Manual Interrupt Operation (continued) 3.6.2 Global Interrupts The set of Global Interrupt Registers (Sections 5.35 to 5.37) contain interrupt status, flag, and enable bits for the FIFO Flags and the System Interrupt con− ditions. The Global Interrupts include the following: •...

  • Page 82: Adc Interrupts

    Pen tek Model 7 16 20 O p erating Manual Page 81 Interrupt Operation (continued) 3.6.3 ADC Interrupts The ADC Interrupt Registers (Sections 6.13 to 6.15) contain interrupt status and control bits for each ADC data acquisition module. The ADC Interrupts include the following for each ADC channel: •...

  • Page 83: Dac Interrupts

    Page 82 Pentek Model 71620 Operating Manual Interrupt Operation (continued) 3.6.4 DAC Interrupts The DAC Interrupt Registers (Sections 7.12 to 7.14) contain interrupt status and control bits for the DAC data processing modules. The DAC Interrupts include the following for the DAC channel: •...

  • Page 84: Fpga Resources Operation

    − 1.5V supply AUX12 On−board registers provide access to the measured data and the System Monitor control registers. All registers are mapped to 71620 memory space 0x08000 to BAR0 0x0815C . See starting at PCI Base Address Register BAR0 Table 3−20 Table 3−21...

  • Page 85: Table 3−20: System Monitor Status Register Addresses

    0x08008 The result of the on−chip V 2.5V supply monitor measurement. CCAUX CCAUX 0x0800C − V These locations are unused in the 71620 AUX8 0x0807C – 0x08064 The result of the V XMC VPWR (5V or 12V) supply measurement. AUX9...

  • Page 86: Table 3−21: System Monitor Control Register Addresses

    Pen tek Model 7 16 20 O p erating Manual Page 85 FPGA Resources Operation (continued) 3.7.1 FPGA System Monitor (continued) The following is the memory map of the System Monitor Control Registers (read and write) including the BAR0 address offset of the register. All reg− isters are 16 bits wide, and the register addresses are in increments of 32 bits.

  • Page 87: I2C Bus Controllers

    C serial buses. Both I C buses are con− trolled using 71620 registers. • I C bus #1 is used internally on the 71620 for several temperature sensors and for control of the Si571 VCXO. Refer to Section 5.31 for the FPGA registers that control this bus.

  • Page 88: Flash Memory Operation

    The FPGA provides a block of addresses reserved for user registers for custom pro− cessing of data from or to the Model 71620 resources. Access these registers using PCI Base Address Register 2 at addresses BAR2 + 0x000000 to 0x3FFFFF .
  • Page 89 Page 88 Pentek Model 71620 Operating Manual This page is intentionally blank Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 90: Chapter 4: Model 71620 Memory Maps

    The Model 71620 is controlled from the XMC baseboard through a PCIe Bus interface. All 71620 resources are configured to be available in PCI Address Space, relative to PCI Base Address Registers as listed in the following table. See...

  • Page 91: Default Fpga Memory Map

    Page 90 Pentek Model 71620 Operating Manual Default FPGA Memory Map The following is the memory map of the default FPGA registers accessible from an XMC baseboard processor, including the PCI BAR0 address offset of the register and a reference to the description for each register. All registers are 32−bits wide, and the register addresses are in increments of 32 bits (four bytes).
  • Page 92 Pen tek Model 7 16 20 O p erating Manual Page 91 Default FPGA Memory Map (continued) Table 4−2: Default FPGA Memory Map (continued) Address Offset Register Access Description BAR0+ Global Control Registers 0x0401C ICAP Section 5.13 0x04020 CDC Control/Status Section 5.14 0x04024 CDC Data...
  • Page 93 Page 92 Pentek Model 71620 Operating Manual Default FPGA Memory Map (continued) Table 4−2: Default FPGA Memory Map (continued) Address Offset Register Access Description BAR0+ A/D Channel 1 Registers 0x10000 Channel Status/Power Management Section 6.2 0x10004 ADC Input Delay Tap Control Section 6.3...
  • Page 94 Pen tek Model 7 16 20 O p erating Manual Page 93 Default FPGA Memory Map (continued) Table 4−2: Default FPGA Memory Map (continued) Address Offset Register Access Description BAR0+ A/D Channel 2 Registers 0x18000 Channel Status/Power Management Section 6.2 0x18004 ADC Input Delay Tap Control Section 6.3...
  • Page 95 Page 94 Pentek Model 71620 Operating Manual Default FPGA Memory Map (continued) Table 4−2: Default FPGA Memory Map (continued) Address Offset Register Access Description BAR0+ A/D Channel 3 Registers 0x20000 Channel Status/Power Management Section 6.2 0x20004 ADC Input Delay Tap Control Section 6.3...
  • Page 96 Pen tek Model 7 16 20 O p erating Manual Page 95 Default FPGA Memory Map (continued) Table 4−2: Default FPGA Memory Map (continued) Address Offset Register Access Description BAR0+ DAC Channel Registers 0x30000 Channel Status/Power Management Section 7.2 0x30004 Output Delay Tap Control Section 7.3 0x30008...
  • Page 97 Page 96 Pentek Model 71620 Operating Manual This page is intentionally blank Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 98: Chapter 5: Global Registers

    Refer to Chapter 4 for the memory maps of all 71620 registers. All register descriptions are given from an XMC baseboard processor’s viewpoint. All registers are 32−bits wide, and the register addresses are in increments of 32 bits (four bytes).

  • Page 99: Link Status Register

    Page 98 Pentek Model 71620 Operating Manual Link Status Register The read−only Link Status Register reports the current status of the 71620 PCIe inter− face link. The following table shows the contents of this register. The subsections following the table provide descriptions of the bits in this register.

  • Page 100: Msi Enabled

    NOTE: Depending on the system it may be less than or equal to the maximum that the 71620 can handle (512 bytes). When setting up ADC DMA link definitions with manual payload size control, it is important that you do not exceed the value read here. Selecting automatic payload size mode will use this value automatically as the default payload size.

  • Page 101: Sel Link Width

    Page 100 Pentek Model 71620 Operating Manual Link Status Register (continued) 5.2.4 SEL LINK WIDTH Bits 15 − 14 These read−only bits indicate the current link width, as follows: x1 link x2 link x4 link x8 link 5.2.5 CORE NOM WIDTH Bits 13 −...

  • Page 102: Link Gen2 Cap

    Pentek Model 71620 Operating Manual Page 101 Link Status Register (continued) 5.2.10 LINK GEN2 CAP Bit 6 This read−only bit indicates if the PCIe link is Gen 2 capable (both the Link Partner and the Device are Gen 2 capable). When read as logic '0' the link is not Gen 2 capable.

  • Page 103: Interrupt Flag Register

    Page 102 Pentek Model 71620 Operating Manual Interrupt Flag Register The Interrupt Flag Register contains one latched bit associated with each 71620 system interrupt condition. The following table shows the contents of this register. Table 5−3, on the next page, describes the interrupt condition associated with each bit.

  • Page 104: Table 5−3: Interrupt Register Bits

    These bits are reserved for user−defined interrupt functions. USER 1 − 6 15 − 10 These are also used by Pentek−installed FPGA IP cores. DAC ACQ MODULE This bit is associated with an interrupt from any of the enabled interrupts in the DAC Interrupt Enable Register (Section 7.12).

  • Page 105: Interrupt Enable Register

    Page 104 Pentek Model 71620 Operating Manual Interrupt Enable Register The Interrupt Enable Register contains one enable bit associated with each 71620 sys− tem interrupt condition. The following table shows the contents of this register. Table 5−3, on the prior page, describes the interrupt condition associated with each bit.

  • Page 106: Byte Swap Register

    Pentek Model 71620 Operating Manual Page 105 Byte Swap Register The Byte Swap Register enables or disables byte swap for all 64−bit PCIe transactions. The following table shows the contents of this register. Table 5−5: Byte Swap Register R/W @ BAR0+0x0000C 31 −...

  • Page 107: Interrupt Control Register

    Page 106 Pentek Model 71620 Operating Manual Interrupt Control Register The Interrupt Control Register controls the 71620 PCIe interrupt. The following table shows the contents of this register. The subsections following the register describe the contents of this register. Table 5−6: Interrupt Control Register R/W @ BAR0+0x00010 31 −...

  • Page 108: Global Register Reset Register

    All bits default to the logic '0' state at power on and reset The GLOBAL RESET bit forcibly resets all registers in the 71620. When set to '1', all control registers will be set to their power−up default values. Note that this bit does not clear linked lists as they are stored in RAM.

  • Page 109: Board Identification Register

    Page 108 Pentek Model 71620 Operating Manual Board Identification Register The read−only Board Identification Register provides the Pentek Model 71620 board identification. Table 5−8: Board Identification Register RO @ BAR0+0x04000 31 − 20 19 − 16 15 − 12 11 − 8 7 −...

  • Page 110: Daughter Board Id Register

    Bits 10 − 8 These three read−only bits indicate the type of Front Panel I/O module installed on the board. This is fixed as ‘ 010 ’ for the Model 71620 board. Rev.: 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 111: Mem Cd Type

    Page 110 Pentek Model 71620 Operating Manual Daughter Board ID Register (continued) 5.9.3 MEM CD TYPE Bits 5 − 4 These read−only bits indicate the type of Memory Module 2 installed on the board. This depends on the memory option, and reads as follows:...

  • Page 112: Fpga Code Type Register

    Pentek Model 71620 Operating Manual Page 111 5.10 FPGA Code Type Register The read−only FPGA Code Type Register identifies the type of FPGA code currently installed in the FPGA for the main board and for each memory module. The following table shows the contents of this register. The subsections following the register describe the contents of this register.

  • Page 113: Mem Ab Code

    Page 112 Pentek Model 71620 Operating Manual 5.10 FPGA Code Type Register (continued) 5.10.3 MEM AB CODE Bits 21 − 20 These two read−only bits indicate the memory type for which the FPGA code was compiled for memory banks A & B. This reads as follows:...

  • Page 114: Fpga Code Revision Register

    Page 113 5.11 FPGA Code Revision Register The read−only FPGA Code Revision Register identifies the Pentek version number of the FPGA code currently installed in the FPGA. The following table shows the contents of this register. The paragraph below the regis−...

  • Page 115: Fpga Date Code Register

    Page 114 Pentek Model 71620 Operating Manual 5.12 FPGA Date Code Register The read−only FPGA Date Code Register identifies the date of the FPGA code currently installed in the FPGA. The following table shows the contents of this register. The paragraphs below the reg−...

  • Page 116: Icap Register

    5.13 ICAP Register The ICAP Register provides a read/write capability for reconfiguring the FPGA. This is the internal reconfiguration port (ICAP Port) for the FPGA, and is for Pentek use only. WARNING!!− Only advanced users who have FPGA reconfiguration experience should use the ICAP port.

  • Page 117: Cdc Control/Status Register

    Page 116 Pentek Model 71620 Operating Manual 5.14 CDC Control/Status Register The CDC Control/Status Register controls CDC7005 reprogramming and indicates the status of the CDC7005 clock synthesizer. The following table shows the contents of this register. The subsections following the table provide descriptions of the bits in this register.

  • Page 118: Prgm

    Pentek Model 71620 Operating Manual Page 117 5.14 CDC Control/Status Register (continued) 5.14.2 PRGM Bit 14 The rising edge of this bit initiates the program sequence for the CDC7005. When cleared to logic '0' (the default setting) the program function does not operate.

  • Page 119: Rst En

    Page 118 Pentek Model 71620 Operating Manual 5.14 CDC Control/Status Register (continued) 5.14.4 RST EN Bit 12 This bit enables reset of the CDC7005 using the CLK B signal. Clear the bit to logic '0' (its default state) to disable the reset from this signal. Set the bit to logic '1' to enable CLK B to reset the CDC7005.

  • Page 120: Cdc Data Register

    The following pages show the format of each CDC Word Register, and the default val− ues programmed by the 71620 at power on and reset (see the CDC7005 Data Sheet in the Model 71620 Supplemental Manual, 809.7x620, for description of each CDC Word register).

  • Page 121: Cdc Word 0 Register

    The Y0, Y1, Y2, Y3, and Y4 designations refer to each of the five LVPECL outputs of the CDC7005. The five outputs are used as follows in the 71620: • Y0 − ADC clocks • Y1 − DAC clocks •...

  • Page 122: Cdc Word 1 Register

    Pentek Model 71620 Operating Manual Page 121 5.15 CDC Data Register (continued) 5.15.2 CDC Word 1 Register Table 5−17: CDC Word 1 Register CP_DIR Bit Name REXT MUX42 MUX41 MUX40 MUX32 MUX31 MUX30 Enable external Function regulate MUX4 Select MUX3 Select...

  • Page 123: Cdc Word 2 Register

    Page 122 Pentek Model 71620 Operating Manual 5.15 CDC Data Register (continued) 5.15.3 CDC Word 2 Register Table 5−18: CDC Word 2 Register 31 − 8 Bit Name Reserved Function Write zeros, Mask when reading Bit Name LOCKW1 LOCKW0 ENBG...

  • Page 124: Clock Control/Status Register

    Pentek Model 71620 Operating Manual Page 123 5.16 Clock Control/Status Register The Clock Control/Status Register manages the CDC7005 output clocks, CDC CLKA (CDC7005 Y0 output) and CDC CLKB (CDC7005 Y1 output) and the FPGA internal clocks, FPGA CLKA and FPGA CLKB, and indicates the status of these clocks.

  • Page 125: Cdc Clkb/Clka Det

    Page 124 Pentek Model 71620 Operating Manual 5.16 Clock Control/Status Register (continued) 5.16.3 CDC CLKB/CLKA DET Bits 10, 8 Each of these read−only bits indicates the status of one of the CDC output clocks, either CDC CLKA or CLKB depending on the bit selected. When the bit is read as logic '0' a valid clock is not detected.

  • Page 126: Sync Bus Control Register 1

    5.17 Sync Bus Control Register 1 The Sync Bus Control Register 1 allows you to configure the Model 71620 as a Clock/ Sync/Gate Master or Slave on the front panel Sync Bus, to select the sources of the Clock, Gate, and Sync output signals, and to control the CDC7005 Clock Generator inputs.

  • Page 127: Sbus Syncb Drv Inv

    Page 126 Pentek Model 71620 Operating Manual 5.17 Sync Bus Control Register 1 (continued) 5.17.1 SBUS SYNCB DRV INV Bit 23 This bit inverts the LVPECL Sync B signal output to the Front Panel Sync Bus. When cleared to logic '0' (the default setting) the signal is not inverted.

  • Page 128: Sbus Gatea Drv Src

    GATEB and SYNCB signals out onto the front panel Sync Bus. When the bit is set to logic '1' this 71620 is the Bus Master and the board drives the GATEB and SYNCB signals out onto the front panel Sync Bus.

  • Page 129: Gatea/Synca Mstr

    GATEA and SYNCA signals out onto the front panel Sync Bus. When the bit is set to logic '1' this 71620 is the Bus Master and the board drives the GATEA and SYNCA signals out onto the front panel Sync Bus.

  • Page 130: Sync Bus Control Register 2

    Pentek Model 71620 Operating Manual Page 129 5.18 Sync Bus Control Register 2 The Sync Bus Control Register 2 allows you to select the source and polarity of the Gate, Sync, and PPS input signals, and select the edge of these signals that will assert an interrupt.

  • Page 131: Pps/Sync/Gate A/B Pol

    Page 130 Pentek Model 71620 Operating Manual 5.18 Sync Bus Control Register 2 (continued) 5.18.2 PPS/SYNC/GATE A/B POL Bits 21 to 16 Each of these bits selects the polarity of one of the Sync Bus signals, either PPS B, SYNC B, GATE B, PPS A, SYNC A, or GATE A, depending on the bit selected.

  • Page 132: Pps A Rcv Src

    Pentek Model 71620 Operating Manual Page 131 5.18 Sync Bus Control Register 2 (continued) 5.18.6 PPS A RCV SRC Bits 7 − 5 These three bits select the input source for the Sync Bus PPS A signal. The settings for these three bits are:...

  • Page 133: Sync Bus Input Delay Tap Control Register

    Page 132 Pentek Model 71620 Operating Manual 5.19 Sync Bus Input Delay Tap Control Register The Sync Bus Input Delay Tap Control Register allows you to program a time delay up to 2.325 nanoseconds, in increments of 75 picoseconds, for the front panel Gate A, Sync A, Gate B, and Sync B input signals.

  • Page 134: Sbus Sync B/A In Dly

    Pentek Model 71620 Operating Manual Page 133 5.19 Sync Bus Input Delay Tap Control Register (continued) 5.19.2 SBUS SYNC B/A IN DLY Bits 28−24/12−8 These bits specify the delay period for the applicable front panel input sig− nal (Sync A or B, depending on the bits selected). The delay period is a 5−bit integer, with the least significant bit equal to 75 picoseconds.

  • Page 135: Sync Bus Input Delay Control Register

    Page 134 Pentek Model 71620 Operating Manual 5.20 Sync Bus Input Delay Control Register The Sync Bus Input Delay Control Register allows you to program a time delay of 1 to 3 clock cycles for the front panel Gate A, Sync A, Gate B, and Sync B input signals. This allows adjustment to timing to compensate for time losses in signal wiring connections.

  • Page 136: User Led Register

    • If the USER LED SRC bits in the LED Control Register, Section 5.22, are set to 00, the USER LED bit in this register turns on or off the USR LED on the 71620 front panel, Section 2.8.2, and the PCB D6 LED, Section 2.4.

  • Page 137: Led Control Register

    Pentek Model 71620 Operating Manual 5.22 LED Control Register The LED Control Register controls several LEDs on the Model 71620 front panel. The following table shows the contents of this register. The subsections following the table provide descriptions of each bit in this register.

  • Page 138: Almn/Ot Led Disable

    Pentek Model 71620 Operating Manual Page 137 5.22 LED Control Register (continued) 5.22.2 ALMn/OT LED DISABLE Bits 11 to 8 Each of these bits enables or disables the front panel TMP LED, Section 2.8.5, in response to the associated FPGA System Monitor alarm signal, either ALM2, ALM1, ALM0, or OT, depending on the bit selected.

  • Page 139: Xxx Mstr Led Disable

    Page 138 Pentek Model 71620 Operating Manual 5.22 LED Control Register (continued) 5.22.6 xxx MSTR LED DISABLE Bits 2 − 0 Each of these bits enables or disables the front panel MAS LED, Section 2.8.3, in response to the associated Sync Bus signal enabled as Master in the Sync Bus Control Register 1, either SBUS B, SBUS A, or CLK, depending on the bit selected.

  • Page 140: Gate A Generate Register

    Gate B Generate Register The Gate B Generate Register generates the GATE B signal on a Model 71620 that is configured as a Sync B/Gate B Master, or on a 71620 that is not connected to an external Sync Bus. Refer to Section 3.5.1...

  • Page 141: Sync A Generate Register

    5.25 Sync A Generate Register The Sync A Generate Register generates the SYNC A signal on a Model 71620 that is configured as a SyncA/GateA Master, or on a 71620 that is not connected to an external Sync Bus. Refer to Section 3.5.2...

  • Page 142: Sync B Generate Register

    Sync B Generate Register The Sync B Generate Register generates the SYNC B signal on a Model 71620 that is configured as a Sync B/Gate B Master, or on a 71620 that is not connected to an external Sync Bus. Refer to Section 3.5.2...

  • Page 143: Test Signal And Timestamp Control Register

    1 = Enable 1 = Reset All bits default to the logic '0' state at power on and reset. * Bits 11−8 are reserved for Pentek factory use only and should not be changed. 5.27.1 TS START TIME LOAD Bit 7 This bit is the Timestamp Time load control bit.

  • Page 144: Ts Synca Rst En

    Pentek Model 71620 Operating Manual Page 143 5.27 Test Signal and Timestamp Control Register (continued) 5.27.3 TS SYNCA RST EN Bit 5 This bit enables the reset of the Timestamp module counters using the SYNC A signal. Clear the bit to logic '0' (its default state) to disable the reset from SYNC A.

  • Page 145: Test Sine A Frequency Control Register

    Page 144 Pentek Model 71620 Operating Manual 5.28 Test Sine A Frequency Control Register The Test Sine A Frequency Control Register determines the frequency of the Test Signal for the ADC input acquisition modules (see Section 3.2). The following table shows the contents of this register.

  • Page 146: Timestamp Start Time Register

    Pentek Model 71620 Operating Manual Page 145 5.30 Timestamp Start Time Register The write−only Timestamp Start Time Register determines the start time for the Time− stamp Module. The following table shows the contents of this register. Table 5−33: Timestamp Start Time Register WO @ BAR0+0x04060 31 −...

  • Page 147: Twsi Port 1 Control/Status Register

    This interface is identified as I C, SMBus, or TWSI bus in different vendors’ literature. Pentek refers to this as the TWSI bus in this manual. The following table shows the contents of this register. The subsections following the table provide descriptions of each bit in this register.

  • Page 148: Rx Fifo Cnt[4:0]

    Pentek Model 71620 Operating Manual Page 147 5.31 TWSI Port 1 Control/Status Register (continued) 5.31.1 RX FIFO CNT[4:0] Bits 28 − 24 These read−only bits indicate the number of bytes received for a TWSI Port 1 read operation. 5.31.2 RX FIFO FULL Bit 22 This read−only bit indicates the status of the TWSI Port 1 Receive FIFO.

  • Page 149: Twsi Addr[6:0]

    Page 148 Pentek Model 71620 Operating Manual 5.31 TWSI Port 1 Control/Status Register (continued) 5.31.7 TWSI ADDR[6:0] Bits 14 − 8 These seven bits specify the bus address of the device on TWSI Bus 1. Each device on the TWSI bus has a separate bus address, as listed in the following table.
  • Page 150 Pentek Model 71620 Operating Manual Page 149 5.31 TWSI Port 1 Control/Status Register (continued) The following steps illustrate the sequences required for writing to or reading from any device on the TWSI Port 1 bus. Note that each device on TSWI Port 1 has subaddresses that access internal register on each device.

  • Page 151: Twsi Port 1 Data Register

    Pentek Model 71620 Operating Manual 5.32 TWSI Port 1 Data Register The TWSI Port 1 Data Register provides the data bits to program the 71620 voltage/ temperature sensor thresholds and the internal Si571 VCXO clock frequency over the board’s serial TWSI Port 1.

  • Page 152: Main Pcb Lm83 Temperature Sensor

    (internal) 50 ° C * These limits are programmed if you run the Pentek ReadyFlow 71620 Hardware Monitor routines for the LM83 using the default values. When any of the four inputs exceeds the HIGH setpoint limit, a red LED on...

  • Page 153: Memory Module Lm73 Temperature Sensors

    Page 152 Pentek Model 71620 Operating Manual 5.32 TWSI Port 1 Data Register (continued) 5.32.3 Memory Module LM73 Temperature Sensors Each optional memory module has a single LM73 temperature sensor that can be programmed on the serial TWSI bus, using LM73 internal registers...

  • Page 154: Twsi Port 2 Control/Status Register

    5.34, allow you to program the XMC interface I C port and the on−board serial EEPROM using the 71620’s serial TWSI (Two−Wire Serial Interface) Port 2. The Con− trol/Status Register, below, contains control and status bits for TWSI bus 2, and the...

  • Page 155: Mga[2:0]

    Page 154 Pentek Model 71620 Operating Manual 5.33 TWSI Port 2 Control/Status Register (continued) 5.33.1 MGA[2:0] Bits 31 − 29 These read−only bits indicate the geographical address for the EEPROM on the XMC interface connected to TWSI Port 2. The EEPROM A2, A1, and A0 address bits are tied to the XMC connector geographical address MGA[2:0] bits.

  • Page 156: Twsi Addr[6:0]

    TWSI ADDR[6:0] Bits 14 − 8 These seven bits specify the bus address of the device on TWSI Bus 2. The 71620 TWSI Port 2 lines are connected to the XMC connector I C serial data and I C serial clock pins. This allows the user to address any I C devices on or connected to the XMC baseboard or carrier that have access to these pins.
  • Page 157 Page 156 Pentek Model 71620 Operating Manual 5.33 TWSI Port 2 Control/Status Register (continued) The following steps illustrate the sequences required for writing to or reading from any device on the TWSI Port 2 bus. Note that each device on TSWI Port 2 has subaddresses that access internal register on each device.

  • Page 158: Twsi Port 2 Data Register

    When DATA DIRECTION = 1, data read from TWSI Port 2. All bits default to the logic '0' state at power on and reset The 71620 TWSI Port 2 lines are connected to the XMC connector MSDA (I C serial data) and MSCL (I C serial clock) pins.

  • Page 159: Cobalt Serial Eeprom

    5−41), is a valid data flag ( 0x00EEC0DE ). Old Format (Table • Following the valid data word is the Cobalt board model number (71620 illustrated in table). • Next are words containing the PCB number, revision, and options for the main PCB module, for the front end I/O module, and for each memory module installed on your product.

  • Page 160: Table 5−41: Eeprom Contents (Old Format)

    Pentek Model 71620 Operating Manual Page 159 5.34 TWSI Port 2 Data Register (continued) 5.34.1 Cobalt Serial EEPROM (continued) The following table shows the contents of the serial EEPROM in the old for− mat used in boards shipped prior to November 2011.

  • Page 161: Table 5−42: Eeprom Contents (New Format)

    Page 160 Pentek Model 71620 Operating Manual 5.34 TWSI Port 2 Data Register (continued) 5.34.1 Cobalt Serial EEPROM (continued) The following table shows the contents of the serial EEPROM in the new format used in boards shipped in November 2011 and later.

  • Page 162: Global Interrupt Enable Register

    Pentek Model 71620 Operating Manual Page 161 5.35 Global Interrupt Enable Register The Global Interrupt Enable Register contains enable bits for each interrupt condition defined. Each bit enables or disables the generation of an interrupt input to the Inter− rupt Flag Register, Section 5.3.

  • Page 163: Table 5−44: Global Interrupt Register Bits

    (Section 5.18). This bit is associated with an interrupt from the LM83 and LM73 BRD TMP Temperature Sensors on the 71620 Main PCB, Front Panel Module, and Memory Module (Sections 5.32.1, 5.32.2, and 5.32.3). Each of these bits is associated with an alarm signal from the FPGA System Monitor.

  • Page 164: Global Interrupt Status Register

    Pentek Model 71620 Operating Manual Page 163 5.36 Global Interrupt Status Register The Global Interrupt Status Register has one read−only status bit associated with each Global interrupt condition (the same bit associations as the Global Interrupt Enable Register, Section 5.35). The following table shows this register’s bit layout.

  • Page 165: Global Interrupt Flag Register

    Page 164 Pentek Model 71620 Operating Manual 5.37 Global Interrupt Flag Register The Global Interrupt Flag Register has one read/clear flag bit associated with each Global interrupt condition (the same bit associations as the Global Interrupt Enable Register, Section 5.35). The following table shows this register’s bit layout.

  • Page 166: Chapter 6: Analog To Digital Channel Registers

    32−bits wide, and the register addresses are in increments of 32 bits. The Model 71620 accepts three analog RF inputs at +8 dBm full scale into 50 ohms on front panel connectors, labeled IN 1, 2, and 3. Each of the three inputs is transformer coupled, digitized by a Texas Instruments ADS5485 200−MHz, 16−bit A/D converter...

  • Page 167: Channel Status/Power Management Registers

    Page 166 Pentek Model 71620 Operating Manual Channel Status/Power Management Registers There are three Channel Status/Power Management Registers, one for each ADC channel, 1, 2, and 3. Each register contains bits that provide power saving functions for elements of that ADC channel.

  • Page 168: Mem Ctrl Dsbl

    Pentek Model 71620 Operating Manual Page 167 Channel Status/Power Management Registers (continued) 6.2.3 MEM CTRL DSBL Bit 6 This bit selects the power saving mode for the ADC channel’s (1, 2, or 3) memory controller. When the bit is cleared to logic '0' (its default state) this channel’s memory controller and the associated memory (if present) are...

  • Page 169: Adc Input Delay Tap Control Registers

    Page 168 Pentek Model 71620 Operating Manual ADC Input Delay Tap Control Registers There are three ADC Input Delay Tap Control Registers, one for each ADC channel (1, 2, and 3). Each register determines the input delay of the digital data from the associ−...

  • Page 170: Adc Data Control Registers

    1 = User Function 1 = Reset 10 = I/Q Packed Mask read 100 = Not used on 71620 Block 11 = I/Q Unpacked 101 = Test Sig Gen Ramp 110 = Test Sig Gen Sinewave 111 = DAC Loopback All bits default to the logic '0' state at power on and reset 6.4.1...

  • Page 171: Ov Led Sel

    Page 170 Pentek Model 71620 Operating Manual ADC Data Control Registers (continued) 6.4.2 OV LED SEL Bit 12 This bit specifies the error source for the front panel ADC OV LED, Section 2.8.8. When this bit is cleared to logic '0' (its default state) the OV LED is driven by an overvoltage condition in the associated ADS5485 (1, 2, or 3).

  • Page 172: Data Src

    Pentek Model 71620 Operating Manual Page 171 ADC Data Control Registers (continued) 6.4.8 DATA SRC Bits 2 − 0 These three bits select the data source for the ADC PACK FIFO (1, 2, or 3). The data sources are: This channel’s ADS5485...

  • Page 173: Adc Rate Divider Registers

    Page 172 Pentek Model 71620 Operating Manual ADC Rate Divider Registers There are three ADC Rate Divider Registers, one for each ADC channel, 1, 2, and 3. This register sets the decimation rate of data samples written to the applicable ADC PACK FIFO.

  • Page 174: Adc Gate/Trigger Control Registers

    Pentek Model 71620 Operating Manual Page 173 ADC Gate/Trigger Control Registers There are three ADC Gate/Trigger Control Registers, one for each ADC channel, 1, 2, and 3. Each register contains bits that select the source and characteristics of the gate/ trigger used to control writing data samples from the ADS5485 to the associated ADC PACK FIFO.

  • Page 175: Trig Linked List Rst

    Page 174 Pentek Model 71620 Operating Manual ADC Gate/Trigger Control Registers (continued) 6.6.2 TRIG LINKED LIST RST Bit 8 This bit resets the Trigger Gen Linked List for this channel’s ADC PACK FIFO (1, 2, or 3). When the bit is cleared to logic '0' (its default state) the Linked List is in run.

  • Page 176: Trig Clr

    Pentek Model 71620 Operating Manual Page 175 ADC Gate/Trigger Control Registers (continued) 6.6.7 TRIG CLR Bit 3 When in Trigger mode (TRIG MODE bit 0 = 1, below), this bit clears any active triggered gate for the channel’s ADC PACK FIFO. When this bit is cleared to logic '0' (its default state) the trigger is in run.

  • Page 177: Adc Trigger Gen Linked List Start Pointer Registers

    Page 176 Pentek Model 71620 Operating Manual ADC Trigger Gen Linked List Start Pointer Registers There are three ADC Trigger Gen Linked List Start Pointer Registers, one for each ADC data channel, 1, 2, and 3. These registers specify the starting Link Number in the linked list for the applicable ADC PACK FIFO trigger sequences.

  • Page 178: Local Gate Generate Registers

    Pentek Model 71620 Operating Manual Page 177 Local Gate Generate Registers There are three Local Gate Generate Registers, one for each ADC data channel, 1, 2, and 3. Each register generates a local GATE signal for the associated ADC channel, which can be used to enable writing to the channel’s ADC PACK FIFO.

  • Page 179: Ram Control Registers

    Page 178 Pentek Model 71620 Operating Manual RAM Control Registers There are three RAM Control Registers, one for each ADC data channel, 1, 2, and 3. These registers contain control bits for operation of QDRII+ SRAM or DDR3 SDRAM for the associated ADC channel.

  • Page 180: Ram Rst

    Pentek Model 71620 Operating Manual Page 179 RAM Control Registers (continued) 6.9.3 RAM RST Bit 4 This bit resets the QDRII+ or DDR3 RAM for the selected ADC channel (1, 2, or 3). When the bit is cleared to logic '0' (its default state) the RAM is in run.

  • Page 181: Input Dc Offset Registers

    Page 180 Pentek Model 71620 Operating Manual 6.10 Input DC Offset Registers There are three Input DC Offset Registers, one for each ADC channel, 1, 2, and 3. The registers define the DC offset for each ADC channel. The following table shows the bit layout of this register. The paragraphs following the table describe these bits.

  • Page 182: Input Gain Trim Registers

    Pentek Model 71620 Operating Manual Page 181 6.11 Input Gain Trim Registers There are three Input Gain Trim Registers, one for each ADC channel, 1, 2, and 3. The registers define the gain trim for each ADC channel. The following table shows the bit layout of this register. The paragraphs following the table describe these bits.

  • Page 183: Adc Dma Control Registers

    Page 182 Pentek Model 71620 Operating Manual 6.12 ADC DMA Control Registers There are three ADC DMA Control Registers, one for each ADC channel, 1, 2, and 3. The registers provide control bits for DMA data transfers from each ADC channel to the PCIe interface.

  • Page 184: Dma At

    Pentek Model 71620 Operating Manual Page 183 6.12 ADC DMA Control Registers (continued) 6.12.2 DMA AT Bits 14 − 13 These two bits select the Address Type of the PCI Express Packet transferred by DMA for this ADC channel (1, 2, or 3). These address types are defined...

  • Page 185: Dma In Fifo Rst

    Page 184 Pentek Model 71620 Operating Manual 6.12 ADC DMA Control Registers (continued) 6.12.7 DMA IN FIFO RST Bit 5 This bit resets the DMA IN FIFO for the selected ADC channel (1, 2, or 3). When the bit is cleared to logic '0' (its default state) the FIFO is in run. When the bit is set to '1' the FIFO is in reset.

  • Page 186: Adc Interrupt Enable Registers

    Pentek Model 71620 Operating Manual Page 185 6.13 ADC Interrupt Enable Registers There are three ADC Interrupt Enable Registers, one for each ADC channel, 1, 2, and 3. Each register contains enable bits for each ADC acquisition module interrupt. Each bit...

  • Page 187: Table 6−13: Adc Interrupt Register Bits

    Page 186 Pentek Model 71620 Operating Manual 6.13 ADC Interrupt Enable Registers (continued) The following table describes the interrupt condition associated with each bit of the ADC Interrupt registers. Table 6−13: ADC Interrupt Register Bits Bit Name Bit Position Interrupt Function...

  • Page 188: Adc Interrupt Flag Registers

    Pentek Model 71620 Operating Manual Page 187 6.14 ADC Interrupt Flag Registers There are three ADC Interrupt Flag Registers, one for each ADC channel, 1, 2, and 3. Each register contains one read/clear flag bit associated with each ADC interrupt con−...

  • Page 189: Adc Interrupt Status Registers

    Page 188 Pentek Model 71620 Operating Manual 6.15 ADC Interrupt Status Registers There are three ADC Interrupt Status Registers, one for each ADC channel, 1, 2, and 3. Each register contains one read−only status bit associated with each ADC interrupt...

  • Page 190: Idelay And Clock Status Registers

    Pentek Model 71620 Operating Manual Page 189 6.16 IDelay and Clock Status Registers There are three read−only IDelay and Clock Status Registers, one for each ADC chan− nel, 1, 2, and 3. The registers provide status bits for the clocks and input delays for the selected ADC channel.

  • Page 191: Mem Iodly Ctrl Rdy

    Page 190 Pentek Model 71620 Operating Manual 6.16 IDelay and Clock Status Registers (continued) 6.16.4 MEM IODLY CTRL RDY Bit 4 This bit indicates the ready state of the memory IODELAY control for the ADC channel (1, 2, or 3) RAM interface. When the bit is read as logic '0' IODELAY control is not ready −...

  • Page 192: Ram Controller Status Registers

    Pentek Model 71620 Operating Manual Page 191 6.17 RAM Controller Status Registers There are three read−only RAM Controller Status Registers, one for each ADC data channel, 1, 2, and 3. These registers contain status bits indicating operating status of QDRII+ or DDR3 RAM FIFO for the associated ADC channel.

  • Page 193: Ram Fifo Aem

    Page 192 Pentek Model 71620 Operating Manual 6.17 RAM Controller Status Registers (continued) 6.17.3 RAM FIFO AEM Bit 5 This bit indicates the Almost Empty state of the QDRII+ or DDR3 RAM FIFO for the selected ADC channel (1, 2, or 3). When the bit is read as logic '0' the FIFO is not Almost Empty.

  • Page 194: Ram Fifo Count Registers

    Pentek Model 71620 Operating Manual Page 193 6.18 RAM FIFO Count Registers There are three ADC RAM FIFO Count Registers, one for each ADC channel, 1, 2, and 3. This read−only register returns the count of 16−bit data samples accessed in the QDRII+ or DDR3 RAM FIFO.

  • Page 195: Adc Dma Status Registers

    Page 194 Pentek Model 71620 Operating Manual 6.19 ADC DMA Status Registers There are three ADC DMA Status Registers, one for each ADC channel, 1, 2, and 3. The registers provide read−only status bits for DMA data transfers from each ADC channel to the PCIe interface.

  • Page 196: Data Rate Detection Control Registers

    Pentek Model 71620 Operating Manual Page 195 6.20 Data Rate Detection Control Registers There are three Data Rate Detection Control Registers, one for each ADC channel, 1, 2, and 3. The registers provide control bits for monitoring the PCI Express data transfer rate of the associated ADC channel.

  • Page 197: Mon Clk Period

    Page 196 Pentek Model 71620 Operating Manual 6.20 Data Rate Detection Control Registers (continued) 6.20.4 MON CLK PERIOD Bits 28 − 0 These bits specify the data rate monitoring period for the selected ADC channel (1, 2, or 3). This is specified in number of 250 MHz PCIe clock cycles, which determines the time period for counting the number of bytes transferred from the associated ADS5485 for this ADC channel.

  • Page 198: Data Rate Detection Value Registers

    Pentek Model 71620 Operating Manual Page 197 6.21 Data Rate Detection Value Registers There are three Data Rate Detection Value Registers, one for each ADC channel, 1, 2, and 3. These read−only registers return the count of data transferred over PCIe from the associated ADS5485 during the specified period.

  • Page 199: Peak Data Rate Detection Value Registers

    Page 198 Pentek Model 71620 Operating Manual 6.22 Peak Data Rate Detection Value Registers There are three Peak Data Rate Detection Value Registers, one for each ADC channel, 1, 2, and 3. These read−only registers return the maximum DATA RATE value measured since the last time this peak was cleared for the associated ADS5485.

  • Page 200: Chapter 7: Digital To Analog Channel Registers

    32−bits wide, and the register addresses are in increments of 32 bits. The 71620 has a single DAC data acquisition module that accepts data from the PCIe interface. The FPGA routes digital data from the PCIe interface by a DMA engine, or from the optional RAM memory, through a DAC output FIFO and then unpacked to the DAC5688 A and B inputs.

  • Page 201: Channel Status/Power Management Register

    Page 200 Pentek Model 71620 Operating Manual Channel Status/Power Management Register The Channel Status/Power Management Register contains bits that provide power saving functions for elements of the DAC data processing channel. The following table shows the contents of these registers. The subsections following the table provide descriptions of the bits in this register.

  • Page 202: Mem Ctrl Dsbl

    Pentek Model 71620 Operating Manual Page 201 Channel Status/Power Management Register (continued) 7.2.3 MEM CTRL DSBL Bit 6 This bit selects the power saving mode for the DAC channel’s memory con− troller. When the bit is cleared to logic '0' (its default state) this channel’s memory controller and the associated memory (if present) are operational.

  • Page 203: Output Delay Tap Control Register

    Page 202 Pentek Model 71620 Operating Manual Output Delay Tap Control Register The Output Delay Tap Control Register determines the output delay of the digital data sent to the DAC5688. The following table shows the contents of this register. Table 7−2: Output Delay Tap Control Register R/W @ BAR0+0x30004 31 −...

  • Page 204: Dac Data Control Register

    010 = Cos & Cos Test Signal Function 1 = Reset Mask when reading 011 = Zero output 100 − 111 = Not used on 71620 All bits default to the logic '0' state at power on and reset 7.4.1 SYNC SEL Bit 13 This bit specifies the sync source for the DAC5688 sync signal.

  • Page 205: Sync Out En

    Page 204 Pentek Model 71620 Operating Manual DAC Data Control Register (continued) 7.4.3 SYNC OUT EN Bit 11 This bit enables the use of the onboard Sync B signal for the DAC5688 SYNC input. When the bit is cleared to logic '0' (its default state) the Sync B signal is not routed to the DAC5688.

  • Page 206: Dac Rate Divider Register

    Pentek Model 71620 Operating Manual Page 205 DAC Rate Divider Register The DAC Rate Divider Register divides the clock to the DAC output FIFO. The following table shows the bit layout of this register. The paragraphs following the table provide descriptions of these bits.

  • Page 207: Dac Gate/Trigger Control Register

    Page 206 Pentek Model 71620 Operating Manual DAC Gate/Trigger Control Register The DAC Gate/Trigger Control Register contains bits that select the source and char− acteristics of the gate/trigger used to control writing data samples to the DAC5688 from the DAC output FIFO.

  • Page 208: Trig Clr

    Pentek Model 71620 Operating Manual Page 207 DAC Gate/Trigger Control Register (continued) 7.6.2 TRIG CLR Bit 3 This bit clears any active trigger for enabling DAC output FIFO writes. When this bit is cleared to logic '0' (its default state) the gate/trigger is in run.

  • Page 209: Output Controller Linked List Start Pointer Register

    Page 208 Pentek Model 71620 Operating Manual Output Controller Linked List Start Pointer Register The Output Controller Linked List Start Pointer Register specifies the starting Link Number in the linked list for the DAC output FIFO trigger sequences. The following tables show the format of these registers.

  • Page 210: Ram Capture Start Address Register

    The RAM Capture Start Address Register specifies the RAM starting address of data to be transferred to QDRII+ SRAM or DDR3 SDRAM by the DAC DMA controller. NOTE: This register is available only on 71620 boards with FPGA Code Revision 4 or greater, as identified in the FPGA Code Revision Register Section 5.11.

  • Page 211: Ram Control Register

    Page 210 Pentek Model 71620 Operating Manual RAM Control Register The RAM Control Register contains control bits for operation of QDRII+ SRAM or DDR3 SDRAM for the DAC data processing. The following table shows the contents of this register. The subsections following the table provide descriptions of each bit in this register.

  • Page 212: Ram Path En

    Pentek Model 71620 Operating Manual Page 211 RAM Control Register (continued) 7.9.4 RAM PATH EN Bit 5 This bit enables data flow from the DMA to the QDRII+ SRAM or DDR3 SDRAM. When this bit is cleared to logic '0' (its default state) RAM is bypassed and DMA data flows directly to the DAC output FIFO.

  • Page 213: Output Gate Delay Register

    Page 212 Pentek Model 71620 Operating Manual 7.10 Output Gate Delay Register The Output Gate Delay Register allows you to program a time delay for the DAC Gate signal. This allows adjustment in output timing to compensate for the latency period in acquiring the data from memory or DMA.

  • Page 214: Dac Dma Control Register

    Pentek Model 71620 Operating Manual Page 213 7.11 DAC DMA Control Register The DAC DMA Control Register provides control bits for DMA data transfers to the DAC channel (DAC DMA FIFO) from the PCIe interface. The following table shows the bit layout of this register. The subsections following the table describe these bits.

  • Page 215: Dma At

    Page 214 Pentek Model 71620 Operating Manual 7.11 DAC DMA Control Register (continued) 7.11.2 DMA AT Bits 14 − 13 These two bits select the Address Type of the PCI Express Packet transferred by DMA for the DAC channel. These address types are defined by the PCI...

  • Page 216: Dma Rst

    Pentek Model 71620 Operating Manual Page 215 7.11 DAC DMA Control Register (continued) 7.11.7 DMA RST Bit 4 This bit resets the DMA engine for the DAC channel. When the bit is cleared to logic '0' (its default state) the DMA is in run. When the bit is set to '1' the DMA engine is in reset.

  • Page 217: Dac Interrupt Enable Register

    Page 216 Pentek Model 71620 Operating Manual 7.12 DAC Interrupt Enable Register The DAC Interrupt Enable Register contains enable bits for each DAC channel inter− rupt. Each bit enables or disables the generation of an interrupt input to the DAC...

  • Page 218: Table 7−12: Dac Interrupt Register Bits

    Pentek Model 71620 Operating Manual Page 217 7.12 DAC Interrupt Enable Register (continued) The following table describes the interrupt condition associated with each bit of the DAC Interrupt registers. Table 7−12: DAC Interrupt Register Bits Bit Name Bit Position Interrupt Function...

  • Page 219: Dac Interrupt Flag Register

    Page 218 Pentek Model 71620 Operating Manual 7.13 DAC Interrupt Flag Register The DAC Interrupt Flag Register contains one read/clear flag bit associated with each DAC interrupt condition (the same bit associations as the DAC Interrupt Enable Regis− ter, Section 7.12;...

  • Page 220: Dac Interrupt Status Register

    Pentek Model 71620 Operating Manual Page 219 7.14 DAC Interrupt Status Register The DAC Interrupt Status Register contains one read−only status bit associated with each DAC interrupt condition (the same bit associations as the DAC Interrupt Enable Register, Section 7.12);...

  • Page 221: Odelay And Clock Status Register

    Page 220 Pentek Model 71620 Operating Manual 7.15 ODelay and Clock Status Register The ODelay and Clock Status Register provides status bits for the clocks and input delays associated with the DAC channel. The following table shows the bit layout of this register. The subsections following the table describe these bits.

  • Page 222: Mem Iodly Ctrl Rdy

    Pentek Model 71620 Operating Manual Page 221 7.15 ODelay and Clock Status Register (continued) 7.15.4 MEM IODLY CTRL RDY Bit 4 This bit indicates the ready state of the memory IODELAY control for the DAC channel. When the bit is read as logic '0' IODELAY control is not ready −...

  • Page 223: Ram Controller Status Register

    Page 222 Pentek Model 71620 Operating Manual 7.16 RAM Controller Status Register The read−only RAM Controller Status Register contains status bits indicating operating status of QDRII+ SRAM or DDR3 SDRAM memory for the DAC channel. The following table shows the contents of this register. The subsections following the table provide descriptions of each bit in this register.

  • Page 224: Ddr Phy Init Done

    Pentek Model 71620 Operating Manual Page 223 7.16 RAM Controller Status Register (continued) 7.16.3 DDR PHY INIT DONE Bit 2 This bit indicates the initialization state of the DDR3 SDRAM memory for the DAC channel. When the bit is read as logic '0' initialization is in prog−...

  • Page 225: Ram Capture Count Register

    Page 224 Pentek Model 71620 Operating Manual 7.17 RAM Capture Count Register There read−only RAM Capture Count Register returns the count of 32−bit data samples present in the QDRII+ SRAM or DDR3 SDRAM. The following table shows the bit layout of this register. The paragraphs following the table provide descriptions of these bits.

  • Page 226: Dac Dma Status Register

    Pentek Model 71620 Operating Manual Page 225 7.18 DAC DMA Status Register The DAC DMA Status Register provides read−only status bits for DMA data transfers to the DAC channel (DAC DMA FIFO) from the PCIe interface. The following table shows the bit layout of this register. The subsections following the table describe these bits.

  • Page 227: All Data Rcvd

    Page 226 Pentek Model 71620 Operating Manual 7.18 DAC DMA Status Register (continued) 7.18.3 ALL DATA RCVD Bit 12 This bit indicates the state of the DMA data for the DAC channel. When the bit is read as logic '0' the DMA is waiting for the transfer completion. When the bit is read as '1' all requested DMA data has been received by the DAC DMA FIFO.

  • Page 228: Dac Serial Address Register

    Pentek Model 71620 Operating Manual Page 227 7.19 DAC Serial Address Register The DAC Serial Address Register specifies the address of the DAC5688 internal register to read from or write to using the DAC Serial Data Register, Section 7.20. NOTE: Set the DAC5688 register address first before reading or writing to the DAC Serial Data Register.

  • Page 229: Table 7−20: Dac5688 Register Addresses

    Page 228 Pentek Model 71620 Operating Manual 7.19 DAC Serial Address Register (continued) The following table lists all internal control registers in the DAC5688 and their address offset. Table 7−20: DAC5688 Register Addresses Register Name Address 0x00 STATUS0 0x01 CONFIG1...

  • Page 230: Dac Serial Data Register

    Pentek Model 71620 Operating Manual Page 229 7.20 DAC Serial Data Register The DAC Serial Address Register reads from or writes to a selected DAC5688 internal control register. Use the DAC Serial Address Register, Section 7.19, to specify the DAC register address that you wish to write to/read from.

  • Page 231: Data Rate Detection Control Register

    Page 230 Pentek Model 71620 Operating Manual 7.21 Data Rate Detection Control Register The Data Rate Detection Control Register provides control bits for monitoring the input data transfer rate over PCIe of the DAC channel. The following table shows the bit lay−...

  • Page 232: Data Rate Detection Value Register

    Pentek Model 71620 Operating Manual Page 231 7.22 Data Rate Detection Value Register The Data Rate Detection Value Register returns the count of data transferred to the DAC5688 during the specified period. The following table shows this register’s bit layout. The paragraphs following this table describe these bits.

  • Page 233: Peak Data Rate Detection Value Register

    Page 232 Pentek Model 71620 Operating Manual 7.23 Peak Data Rate Detection Value Register The Peak Data Rate Detection Value Register returns the maximum DATA RATE value measured since the last time this peak was cleared for the DAC channel.
  • Page 234 The PCI interface on the Model 71620 uses Header Type 00h, which has the layout shown in the table below. This table lists the PCI Configuration Space registers, their functions, and their base address in Configuration Space.

  • Page 235: Table A−2: Pci Base Address Registers

    PCI Configuration Space Registers (continued) In the Model 71620, the first five Base Address Registers of PCI Configuration Space are used to configure the memory maps of board resources and registers. The following table shows the use of these registers in the 71620.

  • Page 236: Introduction

    Page B−1 Appendix B: Sample 71620 Applications Introduction This Appendix provides several Cobalt 71620 XMC module sample signal processing applications, showing the proper setup sequences for these typical applications. The following sample applications are provided:  Using Triggered Acquisition of ADC Data −...

  • Page 237: Using Triggered Acquisition Of Adc Data

    Pentek Model 71620 Operating Manual Using Triggered Acquisition of ADC Data All data acquisition in the Cobalt 71620 XMC module is controlled by a gate signal that allows data to be written to the FIFO. This gate signal can be applied directly in "GATE MODE"...

  • Page 238: Scenario 2

    Pentek Model 71620 Operating Manual Page B−3 Using Triggered Acquisition of ADC Data (continued) B.2.2 Scenario 2 Requirement: After a trigger event − 1) Wait 4000 clock cycles. 2) Acquire 16384 data samples on ADC channel 1. 3) Wait 10,000 clock cycles.

  • Page 239: Using The Adc Dma Engine

    Pentek Model 71620 Operating Manual Using the ADC DMA Engine The Cobalt 71620 XMC module includes an independent DMA engine for each of the three channels of ADC data. The DMA engine includes many special features that can minimize actions required by the host processor while at the same time providing it with useful information about the DMA transfer in side channel packets of meta data.

  • Page 240: Scenario 1

    Upon the comple− tion of data transfer, the 71620 must interrupt the host processor. It is further desired that meta data be sent to the host notifying it of the timestamp of the first data sample.
  • Page 241 Page B−6 Pentek Model 71620 Operating Manual Using the ADC DMA Engine (continued) B.3.1 Scenario 1 (continued)  Scenario 1 Trigger Setup Set the Trigger Clear Set BAR0+0x10010 Bit 3 = '1' bit and set to Trigger Mode Set BAR0+0x10010 Bit 0 = '1’...
  • Page 242 Pentek Model 71620 Operating Manual Page B−7 Using the ADC DMA Engine (continued) B.3.1 Scenario 1 (continued)  Scenario 1 DMA Setup Set BAR0+0x10028 Bit 4 = '1' Reset DMA Linked Set BAR0+0x10028 Bit 4 = '0’ List Engine and FIFO Link Def.
  • Page 243 Upon the completion of data transfer, the 71620 must interrupt the host pro− cessor. It is further desired that meta data be sent to the host notifying it of the amount of data transferred during the gate period, which buffer it went to, and the timestamp of the first data sample.
  • Page 244 Pentek Model 71620 Operating Manual Page B−9 Using the ADC DMA Engine (continued) B.3.2 Scenario 2 (continued) Set BAR0+0x10028 Bit 4 = '1' Reset DMA Linked List Engine and FIFO Set BAR0+0x10028 Bit 4 = '0’ Link Def. Address Function...
  • Page 245 It is desired that the data be transferred to a series of four 16−megabyte data buffers in a circular fashion (Buffer#1−Buffer#4). Upon filling up a buffer, the 71620 must interrupt the host processor. The host processor needs the timestamp information for the beginning of the recording.
  • Page 246 Pentek Model 71620 Operating Manual P age B−11 Using the ADC DMA Engine (continued) B.3.3 Scenario 3 (continued) Set BAR0+0x10010 Bit 3 = '1' Set Trigger Clear bit & set to Trigger Mode Set BAR0+0x10010 Bit 0 = '1’ Hold Trigger Linked List Set BAR0+0x10010 Bit 8 = '1’...
  • Page 247 Page B−12 Pentek Model 71620 Operating Manual Using the ADC DMA Engine (continued) B.3.3 Scenario 3 (continued) (continued from prior page) Flush Packing FIFO Set BAR0+0x10008 Bit 7 = '1' in case it isn’t empty Set BAR0+0x10008 Bit 7 = '0'...

  • Page 248: Scenario 1

    Using the DAC DMA Engine and Linked List Output Controller All DAC data output from the Cobalt 71620 XMC module is controlled by a gate signal that allows data to be read from the DAC output FIFO. The source of data into this FIFO can either be directly from the DMA engine or from QDRII+ or DDR3 RAM waveform storage.
  • Page 249 Page B−14 Pentek Model 71620 Operating Manual Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.1 Scenario 1 (continued) Set BAR0+0x30010 Bit 3 = '1' Set Trigger Clear bit & set to Trigger Mode Set BAR0+0x30010 Bit 0 = '1’...
  • Page 250 Pentek Model 71620 Operating Manual P age B−15 Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.1 Scenario 1 (continued) (continued from prior page) Set BAR0+0x3001C Bit 4 = '1' Reset QDRII+ Storage RAM to start at address 0 Set BAR0+0x3001C Bit 4 = '0’...
  • Page 251 DAC output FIFO. Data in the host proces− sor's memory is set up as a ping−pong buffer. Whenever the 71620 DMA is finished reading one buffer it must interrupt the host processor so that the host processor may begin writing new data into the last used buffer while the next buffer is being read by the 71620.
  • Page 252 Pentek Model 71620 Operating Manual P age B−17 Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.2 Scenario 2 (continued) De−assert gate Set BAR0+0x04048 Bit 0 = '0' generate register bit and Set BAR0+0x30010 Bit 0 = '0'...
  • Page 253 Page B−18 Pentek Model 71620 Operating Manual Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.3 Scenario 3 Requirement: It is required that four unique waveforms of different lengths be stored in QDRII+ RAM. • Waveform #1: 32768 I/Q data samples in length (Resides at host processor memory address Buffer #1) •...
  • Page 254 Pentek Model 71620 Operating Manual P age B−19 Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.3 Scenario 3 (continued) Set BAR0+0x30010 Bit 3 = '1' Set Trigger Clear bit & set to Trigger Mode Set BAR0+0x30010 Bit 0 = '1’...
  • Page 255 Page B−20 Pentek Model 71620 Operating Manual Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.3 Scenario 3 (continued) (continued from prior page) Set BAR0+0x30028 Bit 4 = '1' Reset DMA Linked Set BAR0+0x30028 Bit 4 = '0’...
  • Page 256 Pentek Model 71620 Operating Manual P age B−21 Using the DAC DMA Engine and Linked List Output Controller (cont’d) B.4.3 Scenario 3 (continued) (continued from prior page) Set BAR0+0x30028 Bit 0 = '1' Toggle DMA ADV bit to start the DMA Set BAR0+0x30028 Bit 0 = '0’...
  • Page 257 Page B−22 Pentek Model 71620 Operating Manual This page is intentionally blank Rev. 2.14 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 258 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...

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