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LSI LSI53C895A manual available for free PDF download: Technical Manual
LSI LSI53C895A Technical Manual (364 pages)
PCI to Ultra2 SCSI Controller
Brand:
LSI
| Category:
Controller
| Size: 2.84 MB
Table of Contents
Table of Contents
7
Chapter 1 General Description
17
Typical LSI53C895A System Application
18
New Features in the LSI53C895A
19
Typical LSI53C895A Board Application
19
Benefits of Ultra2 SCSI
20
Benefits of Lvdlink
20
Tolerant ® Technology
21
LSI53C895A Benefits Summary
22
SCSI Performance
22
PCI Performance
23
Integration
24
Ease of Use
24
Flexibility
25
Reliability
25
Testability
26
Chapter 2 Functional Description
27
PCI Functional Description
28
PCI Addressing
28
LSI53C895A Block Diagram
28
PCI Bus Commands and Functions Supported
30
PCI Bus Commands and Encoding Types for the LSI53C895A
30
PCI Cache Mode
35
PCI Cache Mode Alignment
39
SCSI Functional Description
44
SCRIPTS Processor
45
Internal SCRIPTS RAM
46
64-Bit Addressing in SCRIPTS
47
Hardware Control of SCSI Activity LED
47
Designing an Ultra2 SCSI System
48
Prefetching SCRIPTS Instructions
49
Opcode Fetch Burst Capability
50
Load and Store Instructions
50
JTAG Boundary Scan Testing
51
SCSI Loopback Mode
52
Parity Options
52
Bits Used for Parity Control and Generation
53
SCSI Parity Errors and Interrupts
54
SCSI Parity Control
54
Dma Fifo
55
Parity Checking/Generation
55
LSI53C895A Host Interface SCSI Data Paths
57
SCSI Bus Interface
60
HVD Signals
61
8-Bit HVD Wiring Diagram for Ultra2 SCSI
63
Select/Reselect During Selection/Reselection
65
Synchronous Operation
66
Determining the Synchronous Transfer Rate
67
Interrupt Handling
69
Interrupt Routing
76
Chained Block Moves
77
Parallel ROM Interface
81
Parallel ROM Support
82
Serial EEPROM Interface
83
Default Download Mode
83
No Download Mode
84
Alternative SSVID/SSID Loading Mechanism
84
Mode a Serial EEPROM Data Format
84
Power Management
86
Power State D0
87
Power State D1
87
Power States
87
Power State D2
88
Power State D3
88
Chapter 3 Signal Descriptions
89
LSI53C895A Functional Signal Grouping
89
SCSI Bus Interface Signal
89
Power and Ground Signals
89
LSI53C895A Functional Signal Grouping
90
Signal Descriptions
91
Internal Pull-Ups on LSI53C895A Signals
91
LSI53C895A Internal Pull-Ups
91
PCI Bus Interface Signals
92
System Signals
92
Address and Data Signals
93
Interface Control Signals
94
Arbitration Signals
96
Error Reporting Signals
96
Interrupt Signals
97
SCSI GPIO Signals
98
SCSI Bus Interface Signals
99
SCSI Bus Interface Signal
99
SCSI Signals
100
SCSI Control Signals
101
Flash ROM and Memory Interface Signals
102
Test Interface Signals
104
Power and Ground Signals
105
Decode of MAD Pins
108
Chapter 4 Registers
109
PCI Configuration Registers
109
PCI Configuration Register Map
110
SCSI Register Address Map
128
Chapter 5 SCSI SCRIPTS Instruction Set
136
Block Move Instruction
136
Examples of Synchronous Transfer Periods and Rates
141
For SCSI-1
141
Ultra, and Ultra2
142
Maximum Synchronous Offset
143
SCSI Synchronous Data FIFO Word Count
153
SCRIPTS Instructions
157
Second Dword
174
First Dword
209
Second Dword
228
SCSI Information Transfer Phase
233
Read/Write Instructions
235
Second Dword
243
Read/Write Instructions
244
Read-Modify-Write Cycles
245
Read/Write Instructions
246
Transfer Control Instructions
248
SCSI Phase Comparisons
251
Second Dword
254
First Dword
255
Read/Write System Memory from SCRIPTS
256
Third Dword
257
Chapter 6 Electrical Specifications
261
DC Characteristics
261
Absolute Maximum Stress Ratings
262
Operating Conditions
262
LVD Driver
263
Sreq2/, Sack/, Sack2/, Smsg/, Sio/, Scd/, Satn Sbsy/, Ssel/, Srst/
263
LVD Receiver
264
Input Capacitance
264
DIFFSENS SCSI Signal
264
Bidirectional Signals—Mad[7:0], MAS/[1:0], MCE MOE/, MWE/
265
Bidirectional Signals—Ad[31:0], C_BE[3:0]/, FRAME IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
266
Output Signal—Tdo
267
Tolerant Technology Electrical Characteristics
268
Tolerant Technology Electrical Characteristics for SE SCSI Signals
268
Rise and Fall Time Test Condition
269
Hysteresis of SCSI Receivers
270
Output Current as a Function of Output Voltage
271
AC Characteristics
272
External Clock
272
Reset Input
273
PCI and External Memory Interface Timing Diagrams
274
Target Timing
275
PCI Configuration Register Read
276
PCI Configuration Register Write
277
Bit Operating Register/Scripts RAM Read
278
Bit Address Operating Register/Scripts RAM Read
279
Bit Operating Register/Scripts RAM Write
280
Bit Address Operating Register/Scripts RAM Write
281
Initiator Timing
282
Nonburst Opcode Fetch, 32-Bit Address and Data
282
Nonburst Opcode Fetch, 32-Bit Address and Data
283
Burst Opcode Fetch, 32-Bit Address and Data
284
Burst Opcode Fetch, 32-Bit Address and Data
285
Back to Back Read, 32-Bit Address and Data
286
Back to Back Read, 32-Bit Address and Data
287
Back to Back Write, 32-Bit Address and Data
288
Back to Back Write, 32-Bit Address and Data
289
Burst Read, 32-Bit Address and Data
290
Burst Read, 32-Bit Address and Data
291
Burst Read, 64-Bit Address and Data
292
Burst Read, 64-Bit Address and Data
293
Burst Write, 32-Bit Address and Data
294
Burst Write, 32-Bit Address and Data
295
Burst Write, 64-Bit Address and 32-Bit Data
296
Burst Write, 64-Bit Address and 32-Bit Data
297
External Memory Read
299
External Memory Timing
299
External Memory Read
300
External Memory Write
303
External Memory Write
304
Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access Read Cycle
306
Normal/Fast Memory ( ≥ 128 Kbytes) Single Byte Access Write Cycle
307
Normal/Fast Memory ( ≥ 128 Kbytes) Multiple Byte Access Read Cycle
308
Normal/Fast Memory ( ≥ 128 Kbytes) Multiple Byte Access Write Cycle
310
Slow Memory ( ≤ 128 Kbytes) Read Cycle
312
Slow Memory ( ≤ 128 Kbytes) Write Cycle
313
Kbytes ROM Read Cycle
314
Kbyte ROM Write Cycle
315
SCSI Timing Diagrams
316
Initiator Asynchronous Send
316
Initiator Asynchronous Receive
317
Target Asynchronous Send
318
Target Asynchronous Receive
319
SCSI-1 Transfers (Differential 4.17 Mbytes)
320
SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) 50 Mhz Clock
321
Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) 80 Mhz Clock
322
Initiator and Target Synchronous Transfer
323
Package Diagrams
324
LSI53C895A Vs. LSI53C895 Pin/Ball Differences
324
LSI53C895A 272-Pin BGA Top View
325
BGA Pin List by Location
326
BGA Pin List Alphabetically
327
LSI53C895A 208-Pin Plastic Quad Flat Pack
328
Signal Names Vs. Pin Number: 208-Pin Plastic Quad Flat Pack
329
LSI53C895A Vs. LSI53C895 Pin/Ball Differences
331
LSI53C895A Vs. LSI53C895 Pin/Ball Differences
332
LSI53C895A 208 PQFP Mechanical Drawing (Sheet 1 of 2)
334
LSI53C895A 272 PBGA Mechanical Drawing
336
Appendix A Register Summary
337
A.1 LSI53C895A PCI Register Map
337
A.2 LSI53C895A SCSI Register Map
338
Appendix B External Memory Interface Diagram Examples
343
Kbyte Interface with 200 Ns Memory
343
Kbyte Interface with 150 Ns Memory
344
Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte
345
Kbyte Interface with 150 Ns Memory
346
Customer Feedback
357
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