Power Management - LSI LSI53C895A Technical Manual

2.6 Power Management

2-60
EEPROM value is always the first value loaded (if that mechanism is
enabled). The system would then have the opportunity to override the
value loaded from the serial EEPROM.
Below is an example of how the enabling sequence occurs:
1. Ensure that the MAD4 pin is at a logical zero during power-up of the
LSI53C895A. This enables the
2. Write value 0x53 to PCI offset 0x48 using a PCI Configuration Write.
3. Write value 0x59 to PCI offset 0x48 using a PCI Configuration Write.
4. Write value 0x4D to PCI offset 0x48 using a PCI Configuration Write.
The Subsystem ID Access register is now unlocked for a single write.
5. Write the desired subsystem value to offset 0x48–0x4B using a PCI
Configuration Write.
6. Read back the Subsystem register at PCI offset 0x2C–0x2F to verify
the new value written in Step 5.
7. Return to Step 2 to change the subsystem value at offset 0x2C.
Note: During the unlock sequence byte, word, or Dword writes
are allowed, but with the other byte lanes being don't cares.
The following events will reset the lock mechanism:
•
A PCI Reset.
•
Any reads to offset 0x48–0x4B between Steps 2 through 5.
•
Any writes other than the specified data values between Steps 2
through 4.
•
The write of the subsystem value in Step 5.
The LSI53C895A complies with the PCI Bus Power Management
Interface Specification, Revision 1.1. The PCI Function Power States D0,
D1, D2, and D3 are defined in that specification.
D0 is the maximum powered state, and D3 is the minimum powered
state. Power state D3 is further categorized as D3hot or D3cold. A
function that is powered off is said to be in the D3cold power state.
Functional Description
Subsystem ID Access register.