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Epson S1D13704 LCD Controller Module Manuals
Manuals and User Guides for Epson S1D13704 LCD Controller Module. We have
1
Epson S1D13704 LCD Controller Module manual available for free PDF download: Technical Manual
Epson S1D13704 Technical Manual (420 pages)
Embedded Memory Color LCD Controller
Brand:
Epson
| Category:
Controller
| Size: 4.04 MB
Table of Contents
Table of Contents
11
1 Introduction
17
Scope
17
Overview Description
17
2 Features
18
Integrated Frame Buffer
18
CPU Interface
18
Display Support
18
Display Modes
19
Clock Source
19
Miscellaneous
19
Package
19
3 Typical System Implementation Diagrams
20
Figure 3-1: Typical System Diagram (SH-4 Bus)
20
Figure 3-2: Typical System Diagram (SH-3 Bus)
20
Figure 3-3: Typical System Diagram (M68K #1 Bus)
21
Figure 3-4: Typical System Diagram (M68K #2 Bus)
21
Figure 3-5: Typical System Diagram (Generic #1 Bus)
22
Figure 3-6: Typical System Diagram (Generic #2 Bus - E.g. ISA Bus)
22
4 Functional Block Diagram
23
Functional Block Descriptions
23
Figure 4-1: System Block Diagram Showing Data Paths
23
Host Interface
23
Look-Up Table
23
Memory Controller
23
Sequence Controller
23
LCD Interface
24
Look-Up Table
24
Power Save
24
5 Pins
25
Pinout Diagram
25
Figure 5-1: Pinout Diagram
25
Pin Description
26
Host Interface
26
LCD Interface
28
Clock Input
29
Miscellaneous
29
Power Supply
29
Summary of Configuration Options
30
Host Bus Interface Pin Mapping
30
Table 5-1: Summary of Power On/Reset Options
30
Table 5-2: Host Bus Interface Pin Mapping
30
LCD Interface Pin Mapping
31
Table 5-3: LCD Interface Pin Mapping
31
6 C. Characteristics
32
Table 6-1: Absolute Maximum Ratings
32
Table 6-2: Recommended Operating Conditions
32
Table 6-3: Input Specifications
32
Table 6-4: Output Specifications
33
7 C. Characteristics
34
Bus Interface Timing
34
Figure 7-1: SH-4 Timing
34
Interface Timing
34
Table 7-1: SH-4 Timing
35
Figure 7-2: SH-3 Bus Timing
36
Interface Timing
36
Table 7-2: SH-3 Bus Timing
37
Figure 7-3: M68K #1 Bus Timing (MC68000)
38
Motorola M68K #1 Interface Timing
38
Table 7-3: M68K #1 Bus Timing (MC68000)
38
Figure 7-4: M68K #2 Timing (MC68030)
39
Motorola M68K #2 Interface Timing
39
Table 7-4: M68K #2 Timing (MC68030)
39
Figure 7-5: Generic #1 Timing
40
Generic #1 Interface Timing
40
Table 7-5: Generic #1 Timing
40
Figure 7-6: Generic #2 Timing
41
Generic #2 Interface Timing
41
Table 7-6: Generic #2 Timing
41
Clock Input Requirements
42
Table 7-7: Clock Input Requirements
42
Figure 7-7: Clock Input Requirements
42
Display Interface
43
Figure 7-8: LCD Panel Power On/Reset Timing
43
Power On/Reset Timing
43
Figure 7-9: Power Down/Up Timing
44
Power Down/Up Timing
44
Table 7-8: Power Down/Up Timing
44
Figure 7-10: Single Monochrome 4-Bit Panel Timing
45
Single Monochrome 4-Bit Panel Timing
45
Figure 7-11: Single Monochrome 4-Bit Panel A.C. Timing
46
Figure 7-12: Single Monochrome 8-Bit Panel Timing
47
Single Monochrome 8-Bit Panel Timing
47
Figure 7-13: Single Monochrome 8-Bit Panel A.C. Timing
48
Figure 7-14: Single Color 4-Bit Panel Timing
49
Single Color 4-Bit Panel Timing
49
Figure 7-15: Single Color 4-Bit Panel A.C. Timing
50
Figure 7-16: Single Color 8-Bit Panel Timing (Format 1)
51
Single Color 8-Bit Panel Timing (Format 1)
51
Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1)
52
Figure 7-18: Single Color 8-Bit Panel Timing (Format 2)
53
Single Color 8-Bit Panel Timing (Format 2)
53
Figure 7-19: Single Color 8-Bit Panel A.C. Timing (Format 2)
54
Dual Monochrome 8-Bit Panel Timing
55
Figure 7-20: Dual Monochrome 8-Bit Panel Timing
55
Figure 7-21: Dual Monochrome 8-Bit Panel A.C. Timing
56
Dual Color 8-Bit Panel Timing
57
Figure 7-22: Dual Color 8-Bit Panel Timing
57
Figure 7-23: Dual Color 8-Bit Panel A.C. Timing
58
9/12-Bit TFT/D-TFD Panel Timing
59
Figure 7-24: 12-Bit TFT/D-TFD Panel Timing
59
Figure 7-25: TFT/D-TFD A.C. Timing
60
8 Registers
62
Register Mapping
62
Register Descriptions
62
Table 8-1: Panel Data Format
63
Table 8-2: Gray Shade/Color Mode Selection
64
Table 8-3: High Performance Selection
64
Table 8-4: Inverse Video Mode Select Options
65
Table 8-5: Hardware Power Save/Gpio0 Operation
66
Table 8-6: Software Power Save Mode Selection
66
Figure 8-1: Screen-Register Relationship, Split Screen
72
Table 8-7: Look-Up Table Access
73
Table 8-8: Selection of Swivelview Mode
76
Table 8-9: Selection of PCLK and MCLK in Swivelview Mode
77
Frame Rate Calculation
78
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization
79
10 Display Data Formats
79
Table 11-1: Look-Up Table Configurations
80
Figure 11-1: 2-Level Gray-Shade Mode Look-Up Table Architecture
80
Figure 11-2: 4-Level Gray-Shade Mode Look-Up Table Architecture
81
Figure 11-3: 16-Level Gray-Shade Mode Look-Up Table Architecture
81
Figure 11-4: Look-Up Table Bypass Mode Architecture
82
Figure 11-5: 2-Level Color Look-Up Table Architecture
83
Color Display Modes
83
Figure 11-6: 4-Level Color Mode Look-Up Table Architecture
84
Figure 11-7: 16-Level Color Mode Look-Up Table Architecture
85
Figure 11-8: 256-Level Color Mode Look-Up Table Architecture
86
Figure 12-1: Relationship between the Screen Image and the Image Refreshed by S1D13704
87
Swivelview
87
How to Set up Default Swivelview Mode
88
Alternate Swivelview Mode
89
Figure 12-2: Relationship between the Screen Image and the Image Refreshed by S1D13704
89
How to Set up Alternate Swivelview Mode
90
Table 12-1: Default and Alternate Swivelview Mode Comparison
91
Power Save Modes
92
Table 13-1: Power Save Mode Selection
92
Table 13-2: Software Power Save Mode Summary
92
Table 13-3: Hardware Power Save Mode Summary
92
Table 13-4: Power Save Mode Function Summary
93
Figure 13-1: Panel On/Off Sequence
94
Turning off BCLK between Accesses
94
Table 13-5: S1D13704 Internal Clock Requirements
95
Figure 14-1: Mechanical Drawing QFP14
96
14 Mechanical Data
96
Table of Contents
99
1 Introduction
103
2 Initialization
104
Frame Rate Calculation
105
3 Memory Models
107
Display Buffer Location
107
Bit-Per-Pixel (2 Colors/Gray Shades)
107
Bit-Per-Pixel (16 Colors/Gray Shades)
108
Bit-Per-Pixel (4 Colors/Gray Shades)
108
Eight Bit-Per-Pixel (256 Colors)
109
4 Look-Up Table (LUT)
110
Look-Up Table Registers
110
Look-Up Table (LUT) Organization
115
5 Advanced Techniques
121
Virtual Display
121
Examples
122
Registers
122
Examples
124
Registers
124
Split Screen
126
Registers
127
Examples
128
6 LCD Power Sequencing and Power Save Modes
130
LCD Power Sequencing
130
Registers
130
LCD Enable/Disable
131
7 Swivelview
132
Introduction to Swivelview
132
Default Swivelview Mode
132
Alternate Swivelview Mode
133
Registers
135
Limitations
137
Examples
138
8 Identifying the S1D13704
142
9 Hardware Abstraction Layer (HAL)
143
Introduction
143
API for 13704HAL
143
Initialization
143
Miscellaneous HAL Support
145
Advanced HAL Functions
148
Register / Memory Access
151
Drawing
154
Power Save
154
LUT Manipulation
155
10 Sample Code
157
Introduction
157
Sample Code Using the S1D13704 HAL API
157
Sample Code Without Using the S1D13704 HAL API
160
Header Files
168
Table of Contents
181
Introduction
183
Program Requirements
184
Installation
184
Usage
184
13704Cfg
185
Panel Information
186
System
189
LUT Control
190
Open
191
Save
192
Help
193
Exit
193
Comments
194
Table of Contents
235
1 Introduction
239
Features
239
2 Installation and Configuration
240
3 LCD Interface Pin Mapping
242
4 Cpu/Bus Interface Connector Pinouts
243
5 Host Bus Interface Pin Mapping
245
6 Technical Description
246
ISA Bus Support
246
Display Adapter Card Support
246
Expanded Memory Manager
246
Non-ISA Bus Support
247
Embedded Memory Support
247
Decode Logic
247
Clock Input Support
248
LCD Panel Voltage Setting
248
Monochrome LCD Panel Support
248
Color Passive LCD Panel Support
248
Color TFT/D-TFD LCD Panel Support
248
Power Save Modes
249
Adjustable LCD Panel Negative Power Supply
249
Adjustable LCD Panel Positive Power Supply
249
Cpu/Bus Interface Header Strips
250
7 Parts List
251
8 Schematic Diagrams
252
This Page Left Blank
259
1 Introduction
263
General Description
263
2 Direct Connection to the Toshiba TX3912
264
General Description
264
Memory Mapping and Aliasing
265
S1D13704 Configuration and Pin Mapping
265
3 System Design Using the ITE IT8368E PC Card Buffer
266
Hardware Description
266
IT8368E Configuration
267
Memory Mapping and Aliasing
268
S1D13704 Configuration
269
4 Software
270
EPSON LCD Controllers (S1D13704)
271
Toshiba MIPS TX3912 Processor
271
Table of Contents
281
1 Introduction
285
2 Interfacing to the MC68328
286
The MC68328 System Bus
286
Chip-Select Module
286
3 S1D13704 Host Bus Interface
287
Bus Interface Modes
287
Generic #1 Interface Mode
288
MC68K #1 Interface Mode
289
4 MC68328 to S1D13704 Interface
290
Hardware Description
290
Using the MC68K #1 Host Bus Interface
290
Using the Generic #1 Host Bus Interface
291
S1D13704 Hardware Configuration
292
MC68328 Chip Select Configuration
292
5 Software
293
6 References
294
Documents
294
Document Sources
294
Table of Contents
299
1 Introduction
303
2 Interfacing to the NEC VR4102
304
The NEC VR4102 System Bus
304
Overview
304
LCD Memory Access Cycles
305
3 S1D13704 Host Bus Interface
306
Bus Interface Modes
306
Generic #2 Interface Mode
307
4 VR4102 to S1D13704 Interface
309
Hardware Description
309
S1D13704 Hardware Configuration
310
NEC VR4102 Configuration
311
5 Software
312
Table of Contents
317
1 Introduction
321
2 Interfacing to the PC Card Bus
322
The PC Card System Bus
322
Memory Access Cycles
322
PC Card Overview
322
3 S1D13704 Bus Interface
324
Bus Interface Modes
324
Generic #1 Interface Mode
325
4 PC Card to S1D13704 Interface
326
Hardware Connections
326
S1D13704 Hardware Configuration
327
PAL Equations
328
Register/Memory Mapping
328
5 Software
329
Table of Contents
335
1 Introduction
339
2 Interfacing to the MPC821
340
The Mpc8Xx System Bus
340
MPC821 Bus Overview
340
Normal (Non-Burst) Bus Transactions
341
Burst Cycles
342
Memory Controller Module
343
General-Purpose Chip Select Module (GPCM)
343
User-Programmable Machine (UPM)
344
3 S1D13704 Host Bus Interface
345
Host Bus Interface Modes
345
Generic #1 Host Bus Interface Mode
346
4 MPC821 to S1D13704 Interface
347
Hardware Description
347
S1D13704 Hardware Configuration
350
MPC821 Chip Select Configuration
351
Test Software
352
5 Software
354
Table of Contents
359
1 Introduction
363
2 Interfacing to the MCF5307
364
The MCF5307 System Bus
364
Normal (Non-Burst) Bus Transactions
364
Overview
364
Burst Cycles
365
Chip-Select Module
366
3 S1D13704 Bus Interface
367
Bus Interface Modes
367
Generic #1 Interface Mode
368
4 MCF5307 to S1D13704 Interface
369
Hardware Description
369
S1D13704 Hardware Configuration
370
MCF5307 Chip Select Configuration
371
5 Software
372
This Page Left Blank
377
1 Introduction
381
General Description
381
2 Direct Connection to the Philips PR31500/PR31700
382
General Description
382
Memory Mapping and Aliasing
383
S1D13704 Configuration and Pin Mapping
383
3 System Design Using the ITE IT8368E PC Card Buffer
384
Hardware Description
384
IT8368E Configuration
385
This Page Left Blank
393
1 Introduction
397
General Description
397
2 S1D13704/5 Bus Interface
398
Bus Interface Modes
398
Generic #2 Interface Mode
399
3 TMPR3912/22U and S1D13704/5 Interface
400
Hardware Connections
400
Memory Mapping and Aliasing
401
S1D13704/5 Configuration and Pin Mapping
401
4 CPU Module Description
402
Clock Signals
402
Busclk
402
Clki
402
LCD Connectors
402
50-Pin LCD Module Connector, J3
402
Standard Epson LCD Connector, J4
403
LCD Controller
403
LCDPWR Polarity
403
S1D13704 Vs. S1D13705
403
S1D13704\75 Chip Select
403
Introduction
411
Interfacing to an 8-Bit Processor
412
The Generic 8-Bit Processor System Bus
412
S1D13704 Bus Interface
413
Host Bus Pin Connection
413
Generic #2 Interface Mode
414
8-Bit Processor to S1D13704 Interface
415
Hardware Description
415
Register/Memory Mapping
416
S1D13704 Hardware Configuration
416
Software
417
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