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Pin No.
Pin Name
41
WFCK
42
GTOP
43
GFS
44
XPLCK
45
EFMO
46
RAOF
47
MVCI
48
TEST2
49
DIPD
50
DVSS
51
DICV
52
DIFI
53
DIFO
54
AVDD
55
ASYO
56
ASYI
57
BIAS
58
RFI
59
AVSS
60
CLTV
61
PCO
62
FILI
63
FILO
64
PEAK
65
BOTM
66
ABCD
67
FE
68
AUX1
69
VC
70
ADIO
71
TEST3
72
AVDD
73
ADRT
74
ADRB
75
AVSS
76
SE
77
TE
78
AUX2
79
DCHG
80
APC
I/O
WFCK clock (7.35 kHz) signal output
O
(Playback: EFM decoder PLL Recording: EFM encoder PLL) (Not used)
O
"H": Opens playback EFM frame sync protection window (Not used)
O
"H": Playback EFM sync and interpolation protection timing match (Not used)
EFM decoder PLL clock output (98 fs=4.3218 MHz)
O
Falling edge and EFM signal edge match (Not used)
O
EFM signal output (Recording) (Not used)
Internal RAM overflow detection signal output (decoder monitor output)
O
Outputs "H" when the disc rotation exceeds ±4F jitter margin during playback (Not used)
I
Digital-in PLL oscillation input (Fixed at "L")
I
Test pin (Fixed at "L")
Digital-in PLL phase comparison output
O(3)
Internal VCO: (Frequency: Lown"H") External VCO: (Frequency: Lown"L") (Not used)
–
Ground (Digital)
I(A)
Digital-in PLL internal VCO control voltage input
I(A)
Filter input when digital-in PLL internal VCO is used
O(A)
Filter output when digital-in PLL internal VCO is used (Not used)
–
Power supply (+5V) (Analog)
O
Playback EFM full-swing output (L=VSS, H=VDD)
Playback EFM asymmetry comparate voltage input
I(A)
I(A)
Playback EFM asymmetry circuit constant current input
I(A)
Inputs playback EFM RF signal from CXA1981AR (IC101)
–
Ground (Analog)
I(A)
Decoder PLL master clock PLL VCO control voltage input
O(3)
Decoder PLL master clock PLL phase comparison output
I(A)
Decoder PLL master clock PLL filter input
O(3)
Decoder PLL master clock PLL filter output
I(A)
Inputs peak hold signal for light amount signal from CXA1981AR (IC101)
I(A)
Inputs bottom hold signal for light amount signal from CXA1981AR (IC101)
I(A)
Light amount signal from CXA1981AR (IC101)
I(A)
Input of focus error signal from CXA1981AR (IC101)
I(A)
Input of auxiliary signal from CXA1981AR (IC101)
I(A)
Input of middle point voltage (+2.5V) from CXA1981AR (IC101)
O(A)
A/D converter input signal monitor output (Not used)
I(A)
Test input (Fixed at "L")
–
Power supply (+5V) (Analog)
I(A)
A/D converter operation range upper limit voltage input (Fixed at "H")
I(A)
A/D converter operation range lower limit voltage input (Fixed at "L")
–
Ground (Analog)
Input of sled error signal from CXA1981AR (IC101)
I(A)
I(A)
Input of tracking error signal from CXD1981AR (IC101)
I(A)
Auxiliary input 2 (Fixed at "L")
I(A)
Connected to ground
I(A)
Laser APC input (Fixed at "L")
— 81 —
Function
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