Denon AVR-X4100W Service Manual page 180

RX210 Group
R5F5210ABDFP (DIGITAL : IC171)
R5F5210ABDFP Terminal Functions
Pin Symbol
Figure 1.6
1 VREFH
2 P03/DA0
3 VREFL
4 PJ3
5 VCL
6 PJ1
7 MD
8 XCIN
9 XCOUT
10 RES#
11 XTAL/P37
12 VSS
13 EXTAL/P36
14 VCC
15 P35/NMI(input)
16 P34/SCK6/IRQ4
17 P33/RXD6/SSCL6/IRQ3-DS 778_2_HAINT
R01DS0041EJ0150 Rev.1.50
P32/TXD6/SSDA6/IRQ2-
Oct 18, 2013
18
DS
19 P31/IRQ1-DS
20 P30/RXD1/SSCL1/IRQ0DS SCPURXD
21 P27/SCK1
22 P26/TXD1/SSDA1
23 P25
24 P24
25 P23
26 P22/SCK0
27 P21/RXD0/SSCL0
28 P20/TXD0/SSDA0
29 P17/SCK1/IRQ7
30 P16/TXD1/SSDA1/IRQ6
31 P15/RXD1/SSCL1/IRQ5
32 P14/IRQ4
33 P13/SDA/IRQ3
34 P12/SCL/IRQ2
76
PE2
77
PE1
78
PE0
79
PD7
80
PD6
81
PD5
82
PD4
83
PD3
84
PD2
RX210 Group
85
PD1
86
PD0
PLQP0100KB-A
87
P47
88
P46
(100-pin LQFP)
P45 89
P44 90
P43 91
P42 92
P41
93
VREFL0
94
P40
95
VREFH0
96
AVCC0
97
P07
98
AVSS0
99
P05
100
Note: • This figure indicates the power supply pins and I/O port pins. For the pin configuration, see the
table "List of Pins and Pin Functions (100-Pin LQFP)".
Pin Name I/O Pu/Pd LvCnv STBY
Pin Assignments of the 100-Pin LQFP
VREFH
- -
NET/HDMI
O C
VREFL
- -
778_3/778_2
O C
VCL
I -
TX/RX
O C
MD
I -
XCIN
I -
XCOUT
O -
SUB_RESET
I -
XTAL
O -
VSS
- -
EXTAL
I -
VCC
- -
NMI
I -
CEC_OUT
O C
I -
CEC_IN
I -
ACKSIMO
I -
I -
DIRCE
O C
SCPUTXD
O C
DIRDOUT
I -
DIRCLK
O C
REQSOMI
O C
CLKSIMO
I -
SIMO
I -
SOMI
O C
DIRRST
O C
DIRDIN
O C
SUB_BDOWN
I -
NC
O C
NC
O C
778_1_RST
O C
(Top view)
CEC
STBY
+3.3V
- - -
VPLD control pin (H:NET/WiFi/USB/BT,L:HDMI)
- Z L
GND
- - -
Audio data Bus control pin (HDMI input)
- Z -
(H:MN8647781_3,L:MN8647781_2)
Smoothing capacitor connection pin
- - -
NC
- Z -
Single-chip/Micro-processor mode switching (Normal
SCPU
single-chip : L, Rewrite boot program start : H input
- -
3VPu
set)
NC
- - -
NC
- - -
SCPU
Reset input
Z -
3VPu
Oscillator connection
- - -
GND
- - -
Oscillator connection
- - -
+3.3V
- - -
SCPU
NC
- -
3VPu
CEC-D signal output pin
- Z -
HDMI MN8647781(RX) Audio INT input pin
- Z -
SCPU
CEC-D signal input pin
Z -
3VPu
MAIN-SUB ucom communication control pin
- Z -
Data reception input from the external
Pd Z -
DIR control pin(PCM9211)
- Z L
SCPU
Data transmission output to external
Z -
3VPu
DA
DIR control pin(PCM9211)
Z -
3.3Pu
DIR control pin(PCM9211)
- Z L
MAIN-SUB ucom communication control pin
- Z -
MAIN-SUB ucom communication control pin
- Z -
MAIN-SUB ucom communication control pin
- Z -
MAIN-SUB ucom communication control pin
- Z -
DIR control pin(PCM9211)
- O/L L
DIR control pin(PCM9211)
- Z L
Power failure detect(Power failure:L)
- Z -
NC
- Z -
NC
- Z -
HDMI MN8647781(TX) RESET control pin
Pd Z ※
180
1. Overview
50
PC2
49 PC3
48 PC4
47 PC5
46 PC6
45 PC7
44 P50
43 P51
42 P52
41 P53
P54
40
P55
39
PH0
38
PH1
37
PH2
36
PH3
35
P12
34
P13
33
P14
32
P15
31
P16
30
P17
29
P20
28
P21
27
P22
26
Function
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