Aiwa XR-M500 Service Manual page 33

IC, LC78622ED
Pin No. Pin Name I/O
1 DEFI I Defect detection signal (DEF) input.
2 TAI I Test input. A pull-down resistor is built in. Must be connected to 0V.
3 PDO O External VCO control phase comparator output.
4 VVSS — Internal VCO ground. Must be connected to 0V.
5 ISET I PDO output current adjustment resistor connection.
6 VVDD — Internal VCO power supply.
7 FR I VCO frequency range adjustment.
8 VSS — Digital system ground. Must be connected to 0V.
9 EFMO O Slice level control; EFM signal output.
10 EFMIN I Slice level control; EFM signal input.
11 T2 I Test input. A pull-down resistor is built in. Must be connected to 0V.
Disc motor control output.
12, 13 CLV+, CLK- O
Three-value ouput is also possible when specified by microprocessor command.
Rough servo/phase control automatic switching monitor output. Outputs a high level
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14 V/P O
during rough servo and a low level during phase control.
15 HFL I Track detection signal input. This is a Schmitt input.
16 TES I Tracking error signal input. This is a Schmitt input.
17 TOFF O Tracking off output.
18 TGL O Tracking gain switching output. Increase the gain when low.
Track jump output.
19, 20 JP+, JP- O
Three-value output is also possible when specified by microprocessor command.
EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.
21 PCK O
(Not used)
Synchronization signal detection ouput. Outputs a high level when the
22 FSEQ O synchronization FSEQ O signal detected from the EFM signal and the internally
generated synchronization signal agree. (Not used)
23 VDD — Digital system power supply.
24 SL+ O
Serial data command sled signal output terminal from microprocessor.
25 SL- O
26 NC — Not used.
27 PUIN I CD pickup inside limit switch.
28 CD R/W O Serial data command sled signal output terminal from microprocessor.
De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk.
29 EMPH O
(Not used)
30 C2F O C2 flag output. (Not used)
31 DOUT O Digital output (EIAJ format).
32, 33 T3, T4 I Test input. A pull-down resistor is built in. Must be connected to 0V.
34 NC — Unused. Must be left open.
35 MUTEL O Left channel one-bit D/A converter mute output. (Not used)
36 LVDD — Left channel one-bit D/A converter power supply.
37 LCHO O Left channel one-bit D/A converter output.
Description
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Pin No. Pin Name I/O
38 LVSS — Left channel one-bit D/A converter ground. Must be connected to 0V.
39 RVSS — Right channel one-bit D/A converter ground. Must be connected to 0V.
40 RCHO O Right channel one-bit D/A converter output.
41 RVDD — Right channel one-bit D/A converter power supply.
42 MUTER O Right channel one-bit D/A converter mute ouput. (Not used)
43 XVDD — Crystal oscillator power supply.
44 XOUT O
Connections for a 16.934MHz crystal oscillator element.
45 XIN I
46 XVSS — Crystal oscillator ground. Must be connected to 0V.
47 SBSY O Subcode block synchronization signal output. (Not used)
48 EFLG O C1, C2 single and double error correction monitor pin. (Not used)
49 PW O Subcode P, Q, R, S, T, U, V and W output. (Not used)
Subcode frame synchronization signal output. This signal falls when the subcode are in
50 SFSY O
the standby state. (Not used)
Subcode readout clock input. This is a Schmitt input.
51 SBCK I
(Must be connected to 0V when unused)
Output for the 7.35 kHz synchronization signal divided from the crystal oscillator.
52 FSX O
(Not used)
53 WRQ O Subcode Q output standby output.
54 RWC I Readwrite control input. This is a Schmitt input.
55 SQOUT O Subcode Q output.
56 COIN I Command input from the control microprocessor.
Input for both the command input acquisition clock and the SQOUT pin subcode
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57 CQCK I
readout clock input. This is a Schmitt input.
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58 RES I Chip reset pin. This pin must be set low briefly after power is first applied.
59 T11 O Test output. Leave open. (Normally outputs a low level). (Not used)
60 16M O 16.9344 MHz output. (Not used)
61 4.2M O 4.2336 MHz output.
62 T5 I Test input. A pull-down resistor is built in. Must be connected to 0V.
Chip select input. A pull-down resistor is built in. Must be connected to 0V if not
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63 CS I
controlled.
64 T1 I Test input. No pull-down resistor. Must be connected to 0V.
Description
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