Ic Block Diagram; Ic 1002 (Cxd2497R) - JVC GC-QX3U Service Manual

1.4

IC BLOCK DIAGRAM

1.4.1 IC 1002 (CXD2497R)

Pin Descriptions
Pin No. Pin Name I/O
1 V 1 - GND
SS
2 RST I System reset input terminal H: Reset released L: Reset
activated
(Should be activated at power ON, normally.)
(Schmitt trigger input/without protection diode on power
supply side)
3 SNCSL I Sync system switching control input terminal
(with pull-down resistor)
H: CKI sync L: MCKO sync
4 ID O Line identification pulse output terminal in the vertical
direction
5 WEN O Memory write timing pulse output terminal
6 SSGSL I Built-in SSG enable input terminal (with pull-down
resistor)
H: Built-in SSG is effective. L: External sync is effective.
7 V 1 - 3.3V power (for common logic section)
DD
8 V 2 - 3.3V power (for RG terminal)
DD
9 RG O Reset gate pulse output terminal for CCD
10 V 2 - GND
SS
11 V 3 - GND
SS
12 H1 O Clock output terminal for CCD horizontal register
13 H2 O Clock output terminal for CCD horizontal register
14 V 3 - 3.3V to 5.0V power (for H1 and H2 terminals)
DD
15 V 4 - 3.3V power (for CDS system terminals)
DD
16 XSHP O CCD pre-charge level sample/hold pulse output terminal
17 XSHD O CCD data level sample/hold pulse output terminal
18 XRS O Sample/hold pulse output terminal for phase matching in
analog-to-digital conversion
19 PBLK O Pulse output terminal for pulse cleaning during
horizontal and vertical blanking period
20 CLPDM O Pulse output terminal for CCD dummy signal clamping
21 V 4 - GND
SS
22 OBCLP O Pulse output terminal for CCD optical black signal
23 ADCLK O Clock output terminal for analog-to-digital conversion IC
Logical phase is adjustable with the serial interface data
1-8
14 12 13 11 8
OSCI
28
OSCO
27
CKI
26
CKO 25
Pulse Generator
MCKO 30 1/2
Selctor
SNCSL 3
SSI 31
SCK 32
Register
33
SEN
SSGSL
6
SSG
RST 2
TEST1 37
TEST2 48
7 29 1 36 35
Description
9 10 15 16 17 18 21
19 PBLK
20 CLPDM
22 OBCLP
23 ADCLK
24 V 5
SS
4
ID
5
WEN
Latch
41
V1A
43 V1B
39
V2
44
V3A
46
V3B
V Driver
40
V4
47
SUB
VH
42
VM
38
VL
45
34
24 V 5 - GND
SS
25 CKO O Inverter output terminal
26 CKI I Inverter input terminal
27 OSCO O Inverter output terminal for oscillation (If not used,
should be opened or connected to GND through a
capacitor.)
28 OSCI I Inverter input terminal for oscillation (If not used, should
be fixed to "Low".)
29 V 5 - 3.3V power (for common logic section)
DD
30 MCKO O System clock output terminal for signal processing IC
31 SSI I Serial interface data input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
32 SCK I Serial interface clock input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
33 SEN I Serial interface strobe input terminal for setting each IC
mode (Schmitt trigger input/without protection diode on
power supply side)
34 VD I/O Vertical sync signal input/output terminal
35 HD I/O Horizontal sync signal input/output terminal
36 V 6 - GND
SS
37 TEST1 I IC test terminal 1 with pull-down resistor (Should be
fixed to GND normally.)
38 VM - GND (for vertical drivers)
39 V2 O Clock output terminal for CCD vertical register
40 V4 O Clock output terminal for CCD vertical register
41 V1A O Clock output terminal for CCD vertical register
42 VH - 15.0V power (for vertical drivers)
43 V1B O Clock output terminal for CCD vertical register
44 V3A O Clock output terminal for CCD vertical register
45 VL - -7.5V power (for vertical drivers)
46 V3B O Clock output terminal for CCD vertical register
47 SUB O Pulse output terminal for CCD electronic shutter
48 TEST2 I IC test terminal 2 with pull-down resistor (Should be
fixed to GND normally.)