Sony HCD-GN100D Service Manual page 82

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HCD-GN90D/GN100D
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Pin No.
Pin Name
128, 129
VCCA3, VCCA2
130
PDO
131
PDHVCC
132
FDO
133, 134
GNDA2, GNDA1
135
SPO
136
VC2
137
MDIN2
138
MDIN1
139
VCCA1
140
CLVS
141
VSS
142
MDSOUT
143
VDD
144
MDPOUT
145
DEFECT
146
GSCOR
147
EXCK
148
SBIN
149
VSS
150
SCOR
151
WFCK
TE
L 13942296513
152
VDD5V
153
XRCI
154
VDDS
155
C2PO
156
VDD
157
DBCK
158
BCLK
159
DDAT
160
MDAT
161
VSS
162
DLRC
163
LRCK
164
XRST
165
IFS0
166
IFS1
167
XTAL
168
VSS
169
XTA2
170
XTA1
171
VDD
172 to 176
D0 to D4
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I/O
Power supply (+3.3V)
O
Signal output from the charge pump for phase comparator
I
Middle point voltage input terminal for RF PLL
O
Signal output from the charge pump for frequency comparator
Ground
O
Spindle motor control signal output to FAN8035L
I
Middle point voltage (+1.65V) input
I
Spindle motor servo drive signal input
I
MDP input
Power supply (+3.3V)
O
Control signal output for selection the spindle control filter constant at CLVS
Ground
O
Frequency error output terminal of internal CLV circuit
Power supply (+3.3V)
O
Phase error output of internal CLV circuit
I
Defect signal input (Not used)
I
Guard subcode sync (S0+S1) detection signal input from CXD3068Q
O
Subcode serial data reading clock signal output to CXD3068Q
I
Subcode serial data input from CXD3068Q
Ground
I
Subcode sync (S0+S1) detection signal input from CXD3068Q
I
Write frame clock signal input from CXD3068Q
Power supply (+5V)
I
Not used (Pull down)
Power supply (+5V)
I
C2 pointer signal input from CXD3068Q
Power supply (+3.3V)
O
Not used (open)
I
Bit clock signal input from CXD3068Q
O
Not used (open)
I
Serial data input from CXD3068Q
Ground
O
Not used (open)
I
L/R sampling clock signal input from CXD3068Q
I
Reset signal input from CXP973064 ( "L": reset)
I
Not used (connected to ground)
I
Not used (connected to VDD)
I
33.8688 MHz clock signal input from SM8707GV
Ground
O
System clock output (33.8688 MHz)
I
System clock input (33.8688 MHz)
Power supply (+3.3V)
I/O
Two-way data bus with the CXP973064
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Description
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