Table of Contents
Advertisement
QQ
3 7 63 1515 0
Pin No.
Pin Name
57
58
59, 60
HA0, HA2
61
62, 63
HCS0, HCS1
64
65
66 to 69
MDB0 to MDB3
70
71
72
73 to 75
MDB5 to MDB7
76
77
78
79, 80
MA0, MA1
81
82 to 87
MA2 to MA7
88
89
90
91
MA9/MNT0
TE
L 13942296513
92
MA10/MNT1
93
MA11/MNT2
94
95
96, 97
MDB8, MDB9
98
99
100
101, 102
MDBB, MDBC
103
104 to 106
MDBD to MDBF
107
108
109
110
111
112
113, 114
ASF1, AFS2
115
116
117
118, 119
VCCA5, VCCA4
www
120
121
122, 123
GNDA4, GNDA3
.
124
125
126, 127
LPF2, LPF1
http://www.xiaoyu163.com
I/O
XPDI
I/O
Not used (Pull up)
VDDS
—
Power supply (+5V)
I
Not used (Pull up)
VSS
—
Ground (open)
I
Not used (open)
VDD
—
Power supply (+3.3V)
DASP
I/O
Not used (Pull up)
I/O
Two-way data bus with MSM51V1816
VSS
—
Ground
MDB4
I/O
Two-way data bus with MSM51V1816
VDD5V
—
Power supply (+5V)
I/O
Two-way data bus with MSM51V1816
XMWR
O
Write enable signal output to MSM51V1816
VDD
—
Power supply (+3.3V)
XRAS
O
Row address strobe signal output to MSM51V1816
O
Address signal output to MSM51V1816
VSS
—
Ground
O
Not used (open)
VDD
—
Ground
MA8
O
Address signal output to MSM51V1816
VSS
—
Power supply (+3.3V)
O
Address signal output to MSM51V1816
O
Address signal output to MSM51V1816
O
Address signal output to MSM51V1816 (not used)
XMOE
O
Address signal output to MSM51V1816
XCAS
O
Column address strobe signal output to MSM51V1816
I/O
Two-way data bus with MSM51V1816
VSS
—
Ground
MDBA
I/O
Two-way data bus with the MSM51V1816
VDD
—
Power supply (+3.3V)
I/O
Two-way data bus with the MSM51V1816
VDD5V
—
Power supply (+5V)
I/O
Two-way data bus with the MSM51V1816
GFS
O
Guard frame sync signal output to CXP973064
VSS
—
Ground
APEO
O
Absolute phase error signal output
VDD
—
Power supply (+3.3V)
DASYO
O
RF binary signal output
GNDA5
—
Ground
—
Filter connected terminal for selection the constant asymmetry compensation
DASYI
I
Analog signal input after integrated from the RF binary signal
RFDCC
I
Input terminal for adjusting DC cut high-pass filter for RF signal
RFIN
I
RF signal input
—
Power supply (+3.3V)
VCOR1
—
VCO oscillating range setting resistor connected
x
ao
y
VCOIN
I
VCO input
—
Ground
i
LPF5
O
Signal output from the operation amplifier from PLL loop filter
VC1
I
Middle point voltage (+1.65V) input
I
Inverted signal input to the operation amplifier from PLL loop filter
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
HCD-GN90D/GN100D
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
81
Hide quick links:
Advertisement
Table of Contents
