Sony PCM-R500 Service Manual page 48

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Pin No. Pin Name
44 TST4
45 PDO
46 SELC
47 MUTA
48 PLCO
49 PLVR
50 PLRF
51 MSSL
52 RX
53 VDD
54 TX
55 SELA
56 EXSY
57 EXSN
58 F128
59 F256
60 F512
61 ADLF
62 DALF
TE
L 13942296513
63 XT2O
64 XT2I
65 VSS
66 XT3O
67 XT3I
68 FSEN
69 LR03
70 LR02
71 LR01
72 LRCK
73 WCK
74 XBCK
75 BCK
76 ADDT
77 DADT
78 DADO
79 ADDI
80 ADDN
81 ERRI
82 ERRF
83 MNTG
84 D7
85 D6
86 D5
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87 D4
88 D3
89 D2
.
90 VSS
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I/O
I Test pin (Fixed at "L" level.)
O RX-PLL phase comparator output
I Oscillation frequency select signal input (Fixed at "L" level in this set.)
I Mute input. "H" to mute, and REC monitor sound is also muted.
I RX-PLL's external VCO clock input (512fs reference)
Output of phase comparator signal for RX-PLL. (2fs generated from PLL clock.)
O
(Not used in this set.)
Output of phase comparator signal for RX-PLL. (RX SYNC detect signal 2fs)
O
(Not used in this set.)
I Master mode/slave mode slelect. "H" for master mode. (Fixed at "H" level in this set.)
I Digital interface signal input
— +5V
O Digital interface signal output
I Test pin (Fixed at "L" level.)
I/O External sync signal input/output
I/O External sync signal input/output
I/O 128fs signal/256fs signal (high speed) input/output
O 256fs signal/512fs signal (high speed) output (Not used in this set.)
O 512fs signal output (Not used in this set.)
I ADDT, ADDI, ADDN serial data LSB/MSB first select input. "L" for LSB first.
I DADT, DADO serial data LSB/MSB first select input. "L" for LSB first.
O X'tal oscillation circuit 2 output. (Not used in this set.)
I X'tal oscillation circuit 2 input
— Ground
O X'tal oscillation circuit 3 output
I X'tal oscillation circuit 3 input
I F128, BCK, LRCK input/output select input. "H" for output.
O Inverted LR02 signal (Not used in this set.)
Control byte (1). Bit 1: 16BCK delayed LRCK signal when "L" and LRCK clock output by
O
RX-PLL when "H" (Not used in this set.)
O 15BCK delayed LRCK signal
I/O fs/2fs (high speed) signal input/output
O 2fs/4fs (high speed) signal output (Not used in this set.)
O Inverted BCK signal output
I/O 64fs/128fs (high speed) signal input/output
I AD serial data input
O DA serial data output
I DIGITAL OUT audio data input
O DIGITAL IN audio data output
I DIGITAL IN audio data input
I DIGITAL OUT Validity flag data input
O DADT data's interpolation data/descrimination signal output. "H" for interpolation data.
"H" output indicates that error correction status monitor data is being output to D7 to D0.
O
(Not used in this set.)
I/O External RAM data input/output (MSB)
I/O External RAM data input/output
I/O External RAM data input/output
I/O External RAM data input/output
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I/O External RAM data input/output
y
I/O External RAM data input/output
i
— Ground
– 80 –
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2 9
8
Function
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3 6 7 1 3 1 5
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.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9