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Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with
bits A7-A12 to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by
issuing a Mode Register Set command with bits A7 and A9-A12 each set to zero, bit A8
set to one, and bits A0-A6 set to the desired values. A Mode Register Set command
issued to reset the DLL should always be followed by a Mode Register Set command
to select normal operating mode. All other combinations of values for A7-A12 are
reserved for future use and/or test modes. Test modes and reserved states should not
be used as unknown operation or incompatibility with future versions may result.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power
up initialization, and upon returning to normal operation after having disabled the DLL
for the purpose of debug or evaluation. The DLL is automatically disabled when
entering self refresh operation and is automatically re-enabled upon exit of self refresh
operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for
the internal clock to lock to the externally applied clock before a Read command can be
issued. This is the reason for introducing timing parameter tXSRD for DDR SDRAM's
(Exit Self Refresh to Read Command). Non- Read commands can be issued 2 clocks
after the DLL is enabled via the EMRS command (tMRD) or 10 clocks after the DLL is
enabled via self refresh exit command (tXSNR, Exit Self Refresh to Non-Read
Command).
CONFIDENTIAL – DO NOT COPY
Page 7-37
File No. SG-0211
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