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P7382i / P7389i - BLOCK DIAGRAM - PAGE 1/2
KBR0, KBR1, KBR2
H2, H1, H3
J5, J3, J2
to Keyboard
KBC0, KBC1, KBC2
BKLT_EN
K3
to Display
DP_EN_L
A11
SIMPD0
A4
V2
LS1_IN
E9
LS2_IN
E7
F3
BATT_THERM_AD
SIM_TX
B5
SIM_RX
U905
IrDA_EN
B2
VIB_EN
K1
EXT_CHG_EN
C2
HEAD_INT_L
A1
N3
A1
C1
CLK_SELCT
C1
TX_EN
E2
DM_CS
E2
E1
E1
TX_KEY
E3
E3
RX_EN
E4
E4
RX_ACQ
P2
P2
RESET
( SDTX ) BDX
B6
( TX_CLK ) BCLKX
B3
from / to MAGIC
BCLKR
B4
( SDFS ) BFSR
D4
( SDRX ) BDR
A3
15 PIN EXT CONN.
J 600
K2
DSC_EN
13
7
RS232_RX
A5
6
RS232_TX
A6
4
URXD
BATT_FDBK
from Charger
UTXD
3,8
V2
5
IrDA_EN
2
SW_RF
to Antenna Switch
8
EXT_CHG_EN
14
EXT_B+
EXT_B+
5
MAN_TEST_AD
1
GND
DSC_EN_AD
GND
3
DOWNLINL_AD
BATT_THERM_AD
10
GND
ISENSE
15
GND
9
ON / OFF
RESET
11
UPLINK
12
DOWNLINK
MIC
2
1
U902
J504
V2
HEADSET
CON.
R976
HEAD_INT_L
R977
VDDS
C14, F10, G4, H4, K5, P13
VCC_MEMIF
KEYPAD
VDD
A9, A10, C5, K6, K10, M8, M11
DISPLAY
VCCA
WHITE_CAP
INTERFACE
SPI
INTERFACE
SIM
INTER
M
U700
E
FACE
M
O
R
Y
I
CPU
N
CTM
C9
T
MODULE
E
E10
R
B11
F
A
C
D9
E
B9
SERIAL
INTER
DSP
FACE
F1
CTM
STBY_DL
H5
BATT_SER_DATA
PB6
DSC
CHARGE
L7
L6
BATT_FDBK
UART
to J600
SPI
TIMER
INTERF.
INTERFACE
B7
P4
H10
EXT_B+
MIDRATE_1
7
6
MIDRATE_2
U500
IRDA
ISENSE
F5
A7 B7
D9
C7
D6
CHARGE
E8
SPI
SELECT F10
REAL TIME
INTERFACE
CLOCK
F7
SENSE
D10
F6
U900
A1
LEVEL
J7
B2
SENSE
SHIFT
J8
A2
G_CAP2
B3
CNTL.
D9
K7
G6
K10
H8
ON_2
G5
C8
C4
G4
Logic Control
VREF
D2
REG.
C2
V3
REG.
V2
REG.
J2
V1
REG.
VSIM
Interface
REG.
Audio
K1
E18
Codec
C5, B6
A5
VBOOST1
A10, C10
REG.
H6 H7 K9
H9
K6
J9
E1
B10
SR_VCC
SPKR
4
CR902
1-3
5-8
Q938
L901
ALRT
ALRT_VCC
B+
V2
V3
MAGIC SPI
ADDRESS BUS
DATA BUS
SR_VCC
D6, E1
V2
CE2
B2
U702
RESET
CE3
A1
SRAM
R_W
G5
R_W
CE0
CE1
BATT CON.
For description of Midrate Charger
GND
J604
see document on: emeacs.fle.css.mot.com
1
2
4
B+
3
CHRG_EN
BATT+
4
2
3
Q902
CR903
1,2,5,6
1-3
4
6-8
Q905
Q901
STBY_DL
4
3
4,6
2
2
4
Q909
Q904
5
3
7,8
R913
Q900
4
CHRGC
MAIN_FET
BATT+
EXT_B+
CLK
1
J803
RESET
SIM
2
SIM_I/O
Con.
6
4
3
VSIM1
LS1_IN
LS2_IN
SIM_TX
SIM_RX
PWR_SW
STBY_DL
G9
VREF
2.775V,for Magic
B5
V3
1,8V, for WhiteCap
J5
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
A6
V1
5.0V, for DSC Bus, Negative Voltage Regulator
C6
VSIM1
3.0 or 5.0V, for SIM Card Circuit
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
to Backlight
ALRT_VCC
to MAGIC
A4, E1, F5
B4
U701
EPROM
EEPROM
B3
D7
F8
4
1
U904
-10V
KBR0, KBR1, KBR2
to WhiteCap
V1
U903
-5V
2
KBC0, KBC1, KBC2
1
BATT_SER_DATA
BATT_THERM_AD
VREF
DEEP SLEEP
V1_SW
V1
V2
CIRCUIT
from WhiteCap
( WhiteCap )
VIB_EN
B+
J902
A0
3
D0-D7
5-12
V1-V5
INT.
C702-C706
DIV.
V2
13
2
RESET
GND
14
R_W
4
DP_EN_L
15
( -10V )
1
KEYPAD
PWR_SW
from G CAP2
BACK
ALERT_VCC
LIGHT
from G CAP2
C
B
Q907
BKLT_EN
E
J5001 J5002
1
4
U501
5
VIBRA CON.
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
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