Momory Chip Selection Circuit - Casio CE-7000 Service Manual

6-4. Memory chip selection circuit
The RAM chip select signals made by the following circuit.
There are 4 chip enable signal lines for RAM selection and 3 chip enable signal lines for
Flash ROM selection (including Memory cassette).
RB1
RB2
RB3
RB4/CB1
FB1
RAM enable
ARC RESET
RAM1 selection
The RAM1 is selected by the RAM enable signal "H" and the 2CS signal " L" of output pin
No.13 . The 2SC signal becomes "L" when the CPU address is as follows:
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
L L H L X
2
Also, the 3SC signal becomes "L" when the CPU address is as follows:
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
L L H H
3
Therefore, the RAM1 CE will active when the CPU adress is from 20000H to 3FFFFH with
RAM enable signal "H".
Flash ROM1 selection
The Flash 1 CE will active by the IC25 output pin No.3. This is inverted signal of A19.
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
H L L L
8
Therefore, the Flash1 CE will active when the CPU adress is from 80000H to FFFFFH.
X X X X X
X
X X X X X X
X
X X X X X X
X
- 13 -
A8 A7 A6 A5
X X X X X
X X
A8 A7 A6 A5
X X X X X
X X
A8 A7 A6 A5
X X X X X
X X
RAM1 CE
RAM2 CE
RAM3 CE
RAM4 CE
RAM1 CE is for
RAM 1 chip enable signal.
A4 A3 A2 A1 A0
X X X X X
X
A4 A3 A2 A1 A0
X X X X X
X
A4 A3 A2 A1 A0
X X X X X
X